/********************************************************************/
/* evm5505.gel                                                      */
/* Version 0.32                                                     */
/*                                                                  */
/* This GEL file is to be used with the TMS320C25505 DSP.           */
/* Changes may be required to support specific hardware designs.    */
/*                                                                  */
/* Code Composer Studio supports six reserved GEL functions that    */
/* automatically get executed if they are defined. They are:        */
/*                                                                  */
/* StartUp()              - Executed whenever CCS is invoked        */
/* OnReset()              - Executed after Debug->Reset CPU         */
/* OnRestart()            - Executed after Debug->Restart           */
/* OnPreFileLoaded()      - Executed before File->Load Program      */
/* OnFileLoaded()         - Executed after File->Load Program       */
/* OnTargetConnect()      - Executed after Debug->Connect           */
/*                                                                  */
/********************************************************************/

StartUp()
{
    C5505_MapInit();
}

/*--------------------------------------------------------------*/
/* OnTargetConnect() -- this function is called after a target  */
/* connect.                                                     */
/*--------------------------------------------------------------*/
OnTargetConnect()
{
    GEL_Reset();
    ProgramPLL_100MHz();

    GEL_TextOut("Target Connection Complete.\n"); 
}

/*--------------------------------------------------------------*/
/* OnPreFileLoaded()                                            */
/* This function is called automatically when the 'Load Program'*/
/* Menu item is selected.                                       */
/*--------------------------------------------------------------*/
OnPreFileLoaded()
{
    /* Reset the CPU to clean up state */
    GEL_Reset();
}

/*--------------------------------------------------------------*/
/* OnRestart()                                                  */
/* This function is executed before a file is restarted. Disable*/
/* interrupts and DMA from the current program so pending       */
/* events and transfers don't interfere with the new program.   */
/*--------------------------------------------------------------*/
OnRestart()
{
    /* Disable interrupts */
    *(int*)0x0003 = *(int*)0x0003 | 0x0800; // Set INTM
    *(int*)0x0000 = 0;      // Clear IER0
    *(int*)0x0000 = 0;      // Clear IER1
}

/*--------------------------------------------------------------*/
/* OnReset()                                                    */
/* This function is called by CCS when you do Debug->Resest.    */
/* The goal is to put the C55xx into a known good state with    */
/* respect to cache, dma and interrupts.                        */
/*--------------------------------------------------------------*/
OnReset( int nErrorCode )
{
  /* Uncomment the following functions to reset the peripheral
   * and reconfig the pll for a more complete chip reset and
   * reconfigure. If using off-chip memory then also include
   * functions to setup the emif.
   */

  /*Peripheral_Reset();
   *ProgramPLL_12p288MHz();
   *SDRAM_INIT();
   */
}

/*--------------------------------------------------------------*/
/* OnFileLoaded()                                               */
/* This function is called by CCS when you do File->Load Program*/
/* The goal is to do in post file loaded configuration that may */
/* be needed.                                                   */
/*--------------------------------------------------------------*/
OnFileLoaded()
{
}

#define ESCR     0x1c33

#define SDTIMR1  0x1020 
#define SDTIMR2  0x1021 
#define SDCR1    0x1008 
#define SDCR2    0x1009
#define SDSRETR  0x103C
#define	SDRCR    0x100C

#define PRCR    0x1C05 
#define PCGCR1  0x1c02
#define PCGCR2  0x1c03
#define PSRCR   0x1c04

#define CCR2    0x1c1f
#define CGCR1   0x1c20
#define CGCR2   0x1c21
#define CGCR3   0x1c22
#define CGCR4   0x1c23
#define CCSSR   0x1c24

menuitem "C5505EVM_Configuration";
hotmenu CPU_Reset()
{
    GEL_Reset();
    GEL_TextOut("CPU Reset Complete.\n");
}

hotmenu C5505EVM_Init()
{
    GEL_Reset();
    C5505_MapInit();
    GEL_TextOut("C5505EVM Initialization Complete.\n");
}

hotmenu SetPLL_12p288MHz() {
    ProgramPLL_12p288MHz();
}

hotmenu SetPLL_40MHz() {
    ProgramPLL_40MHz();
}

hotmenu SetPLL_60MHz() {
    ProgramPLL_60MHz();
}

hotmenu SetPLL_75MHz() {
    ProgramPLL_75MHz();
}

hotmenu SetPLL_100MHz() {
    ProgramPLL_100MHz();
}

hotmenu SetClkoutSrcToSysclk(){
    *(short *)CCSSR@IO = 0xB;
    GEL_TextOut("Configure PLL (100.00 MHz).\n");
}


hotmenu Peripheral_Reset() {
    int i;

    *(short *)PSRCR@IO = 0x0020;
    *(short *)PRCR@IO  = 0x00BB;

    for(i=0;i<0xff;i++);

    GEL_TextOut("Reset Peripherals is complete.\n");
}


/* mSDRAM = MT48H4M16LF-8 */
/* Timings based on EMIF clk = 100MHz */
menuitem "SDRAM_Configuration";
hotmenu SDRAM_INIT() {
    int i;

    /* reset EMIF */
    *(short *)PRCR@IO = 0x0002;
    for(i=0;i<0xff;i++);

	/* enable word writes to EMIF regs */
    *(short *)ESCR@IO = 0;

    /* step 1 */
    *(short *)SDTIMR1@IO = 0x4710;
    *(short *)SDTIMR2@IO = 0x3911;
    *(short *)SDSRETR@IO = 0x0007;

    /* step 2 */
    *(short *)SDRCR@IO = 0x04E3;
    
    /* step 3 */
    *(short *)SDCR1@IO = 0x4720;
    *(short *)SDCR2@IO = 0x0001;

    /* step 4 */
    for(i=0;i<0xff;i++);

    /* step 5 */
    *(short *)SDRCR@IO = 0x061A;

    GEL_TextOut("SDRAM Initilization Complete.\n");
}

// ***************************************************************************

/* Memory map based on MP/MC value (assume MP/MC = 0).    */
C5505_MapInit() {
    GEL_MapOn();
    GEL_MapReset();

    /*Program Space*/

    /* DARAM */
    GEL_MapAdd(0x0000C0,0,0x001F40,1,1);    /* DARAM0 */
    GEL_MapAdd(0x002000,0,0x002000,1,1);    /* DARAM1 */
    GEL_MapAdd(0x004000,0,0x002000,1,1);    /* DARAM2 */
    GEL_MapAdd(0x006000,0,0x002000,1,1);    /* DARAM3 */
    GEL_MapAdd(0x008000,0,0x002000,1,1);    /* DARAM4 */
    GEL_MapAdd(0x00A000,0,0x002000,1,1);    /* DARAM5 */
    GEL_MapAdd(0x00C000,0,0x002000,1,1);    /* DARAM6 */
    GEL_MapAdd(0x00E000,0,0x002000,1,1);    /* DARAM7 */

    /* SARAM */
    GEL_MapAdd(0x010000,0,0x002000,1,1);    /* SARAM0 */
    GEL_MapAdd(0x012000,0,0x002000,1,1);    /* SARAM1 */
    GEL_MapAdd(0x014000,0,0x002000,1,1);    /* SARAM2 */
    GEL_MapAdd(0x016000,0,0x002000,1,1);    /* SARAM3 */
    GEL_MapAdd(0x018000,0,0x002000,1,1);    /* SARAM4 */
    GEL_MapAdd(0x01A000,0,0x002000,1,1);    /* SARAM5 */
    GEL_MapAdd(0x01C000,0,0x002000,1,1);    /* SARAM6 */
    GEL_MapAdd(0x01E000,0,0x002000,1,1);    /* SARAM7 */
    GEL_MapAdd(0x020000,0,0x002000,1,1);    /* SARAM8 */
    GEL_MapAdd(0x022000,0,0x002000,1,1);    /* SARAM9 */
    GEL_MapAdd(0x024000,0,0x002000,1,1);    /* SARAM10 */
    GEL_MapAdd(0x026000,0,0x002000,1,1);    /* SARAM11 */
    GEL_MapAdd(0x028000,0,0x002000,1,1);    /* SARAM12 */
    GEL_MapAdd(0x02A000,0,0x002000,1,1);    /* SARAM13 */
    GEL_MapAdd(0x02C000,0,0x002000,1,1);    /* SARAM14 */
    GEL_MapAdd(0x02E000,0,0x002000,1,1);    /* SARAM15 */
    GEL_MapAdd(0x030000,0,0x002000,1,1);    /* SARAM16 */
    GEL_MapAdd(0x032000,0,0x002000,1,1);    /* SARAM17 */
    GEL_MapAdd(0x034000,0,0x002000,1,1);    /* SARAM18 */
    GEL_MapAdd(0x036000,0,0x002000,1,1);    /* SARAM19 */
    GEL_MapAdd(0x038000,0,0x002000,1,1);    /* SARAM20 */
    GEL_MapAdd(0x03A000,0,0x002000,1,1);    /* SARAM21 */
    GEL_MapAdd(0x03C000,0,0x002000,1,1);    /* SARAM22 */
    GEL_MapAdd(0x03E000,0,0x002000,1,1);    /* SARAM23 */
    GEL_MapAdd(0x040000,0,0x002000,1,1);    /* SARAM24 */
    GEL_MapAdd(0x042000,0,0x002000,1,1);    /* SARAM25 */
    GEL_MapAdd(0x044000,0,0x002000,1,1);    /* SARAM26 */
    GEL_MapAdd(0x046000,0,0x002000,1,1);    /* SARAM27 */
    GEL_MapAdd(0x048000,0,0x002000,1,1);    /* SARAM28 */
    GEL_MapAdd(0x04A000,0,0x002000,1,1);    /* SARAM29 */
    GEL_MapAdd(0x04C000,0,0x002000,1,1);    /* SARAM30 */
    GEL_MapAdd(0x04E000,0,0x002000,1,1);    /* SARAM31 */

    /* External-Memory */
    GEL_MapAdd(0x050000,0,0x7B0000,1,1);    /* External-SDRAM */
    GEL_MapAdd(0x800000,0,0x400000,1,1);    /* External-Async */
    GEL_MapAdd(0xC00000,0,0x200000,1,1);    /* External-Async */
    GEL_MapAdd(0xE00000,0,0x100000,1,1);    /* External-Async */
    GEL_MapAdd(0xF00000,0,0x0E0000,1,1);    /* External-Async */

    /* ROM */
    GEL_MapAdd(0xFE0000,0,0x008000,1,0);    /* SAROM0 */
    GEL_MapAdd(0xFE8000,0,0x008000,1,0);    /* SAROM1 */
    GEL_MapAdd(0xFF0000,0,0x008000,1,0);    /* SAROM2 */
    GEL_MapAdd(0xFF8000,0,0x008000,1,0);    /* SAROM3 */

    /* Data Space */

    /* DARAM */
    GEL_MapAdd(0x000000,1,0x000060,1,1);    /* MMRs */
    GEL_MapAdd(0x000060,1,0x000FA0,1,1);    /* DARAM0 */
    GEL_MapAdd(0x001000,1,0x001000,1,1);    /* DARAM1 */
    GEL_MapAdd(0x002000,1,0x001000,1,1);    /* DARAM2 */
    GEL_MapAdd(0x003000,1,0x001000,1,1);    /* DARAM3 */
    GEL_MapAdd(0x004000,1,0x001000,1,1);    /* DARAM4 */
    GEL_MapAdd(0x005000,1,0x001000,1,1);    /* DARAM5 */
    GEL_MapAdd(0x006000,1,0x001000,1,1);    /* DARAM6 */
    GEL_MapAdd(0x007000,1,0x001000,1,1);    /* DARAM7 */

    /* SARAM */
    GEL_MapAdd(0x008000,1,0x001000,1,1);    /* SARAM0 */
    GEL_MapAdd(0x009000,1,0x001000,1,1);    /* SARAM1 */
    GEL_MapAdd(0x00A000,1,0x001000,1,1);    /* SARAM2 */
    GEL_MapAdd(0x00B000,1,0x001000,1,1);    /* SARAM3 */
    GEL_MapAdd(0x00C000,1,0x001000,1,1);    /* SARAM4 */
    GEL_MapAdd(0x00D000,1,0x001000,1,1);    /* SARAM5 */
    GEL_MapAdd(0x00E000,1,0x001000,1,1);    /* SARAM6 */
    GEL_MapAdd(0x00F000,1,0x001000,1,1);    /* SARAM7 */
    GEL_MapAdd(0x010000,1,0x001000,1,1);    /* SARAM8 */
    GEL_MapAdd(0x011000,1,0x001000,1,1);    /* SARAM9 */
    GEL_MapAdd(0x012000,1,0x001000,1,1);    /* SARAM10 */
    GEL_MapAdd(0x013000,1,0x001000,1,1);    /* SARAM11 */
    GEL_MapAdd(0x014000,1,0x001000,1,1);    /* SARAM12 */
    GEL_MapAdd(0x015000,1,0x001000,1,1);    /* SARAM13 */
    GEL_MapAdd(0x016000,1,0x001000,1,1);    /* SARAM14 */
    GEL_MapAdd(0x017000,1,0x001000,1,1);    /* SARAM15 */
    GEL_MapAdd(0x018000,1,0x001000,1,1);    /* SARAM16 */
    GEL_MapAdd(0x019000,1,0x001000,1,1);    /* SARAM17 */
    GEL_MapAdd(0x01A000,1,0x001000,1,1);    /* SARAM18 */
    GEL_MapAdd(0x01B000,1,0x001000,1,1);    /* SARAM19 */
    GEL_MapAdd(0x01C000,1,0x001000,1,1);    /* SARAM20 */
    GEL_MapAdd(0x01D000,1,0x001000,1,1);    /* SARAM21 */
    GEL_MapAdd(0x01E000,1,0x001000,1,1);    /* SARAM22 */
    GEL_MapAdd(0x01F000,1,0x001000,1,1);    /* SARAM23 */
    GEL_MapAdd(0x020000,1,0x001000,1,1);    /* SARAM24 */
    GEL_MapAdd(0x021000,1,0x001000,1,1);    /* SARAM25 */
    GEL_MapAdd(0x022000,1,0x001000,1,1);    /* SARAM26 */
    GEL_MapAdd(0x023000,1,0x001000,1,1);    /* SARAM27 */
    GEL_MapAdd(0x024000,1,0x001000,1,1);    /* SARAM28 */
    GEL_MapAdd(0x025000,1,0x001000,1,1);    /* SARAM29 */
    GEL_MapAdd(0x026000,1,0x001000,1,1);    /* SARAM30 */
    GEL_MapAdd(0x027000,1,0x001000,1,1);    /* SARAM31 */

    /* External-Memory */
    GEL_MapAdd(0x028000,1,0x3D8000,1,1);    /* External-SDRAM */
    GEL_MapAdd(0x400000,1,0x200000,1,1);    /* External-Async */
    GEL_MapAdd(0x600000,1,0x100000,1,1);    /* External-Async */
    GEL_MapAdd(0x700000,1,0x080000,1,1);    /* External-Async */
    GEL_MapAdd(0x780000,1,0x070000,1,1);    /* External-Async */

    /* ROM */
    GEL_MapAdd(0x7F0000,1,0x004000,1,0);    /* SAROM0 */
    GEL_MapAdd(0x7F4000,1,0x004000,1,0);    /* SAROM1 */
    GEL_MapAdd(0x7F8000,1,0x004000,1,0);    /* SAROM2 */
    GEL_MapAdd(0x7FC000,1,0x004000,1,0);    /* SAROM3 */

    /* IO Space */
    GEL_MapAdd(0x0000,2,0xFFFF,1,1);        /* XPORT */
}

ProgramPLL_12p288MHz() {
    int i;

    GEL_TextOut("Configure PLL (12.288 MHz).\n");
    // Enable clocks to all peripherals
    *(short *)PCGCR1@IO = 0x0;
    *(short *)PCGCR2@IO = 0x0;

    // bypass PLL
    *(short *)CCR2@IO = 0x0;

    // set CLR_CNTL = 0
    *(short *)CGCR1@IO = *(short *)CGCR1@IO & 0x7FFF;

	if(ClkSelSetting()) {  // CLKIN source (12MHz)
        *(short *)CGCR2@IO = 0x016E;  //RDBYPASS=0, ML=0, RDRATIO=16Eh(366)
        *(short *)CGCR4@IO = 0x0200;  //OUTDIVEN=1, OUTDIV2BYPASS=0, ODRATIO=0
        *(short *)CGCR3@IO = 0x0806;  //INIT = 0x0806
        *(short *)CGCR1@IO = 0x82ED;  //CLR_CNTL=1, PLL_STANDBY=0, PLL_PWRDN=0, MH=2EDh  
	}
	else {  // RTC osc source (32.768kHz)
        *(short *)CGCR2@IO = 0x8000;  //RDBYPASS=1, ML=0, RDRATIO=0
        *(short *)CGCR4@IO = 0x0200;  //OUTDIVEN=1, OUTDIV2BYPASS=0, ODRATIO=0
        *(short *)CGCR3@IO = 0x0806;  //INIT = 0x0806
        *(short *)CGCR1@IO = 0x82ED;  //CLR_CNTL=1, PLL_STANDBY=0, PLL_PWRDN=0, MH=2EDh  
	}

    // wait for PLL lock
    for(i=0;i<0xff;i++);

    // Switch to PLL clk
    *(short *)CCR2@IO = 0x1;

    GEL_TextOut("PLL Init Done (12.288 MHz).\n");
}

ProgramPLL_40MHz() {
    int i;

    GEL_TextOut("Configure PLL (40.04 MHz).\n");
    // Enable clocks to all peripherals
    *(short *)PCGCR1@IO = 0x0;
    *(short *)PCGCR2@IO = 0x0;

    // bypass PLL
    *(short *)CCR2@IO = 0x0;

	// set CLR_CNTL = 0
    *(short *)CGCR1@IO = *(short *)CGCR1@IO & 0x7FFF;

	if(ClkSelSetting()) {  // CLKIN source (12MHz)
        *(short *)CGCR2@IO = 0x016E;  //RDBYPASS=0, ML=0, RDRATIO=16Eh(366)
	    *(short *)CGCR4@IO = 0x0300;
	    *(short *)CGCR3@IO = 0x0806;
	    *(short *)CGCR1@IO = 0x8262;
	}
	else {  // RTC osc source (32.768kHz)
	    *(short *)CGCR2@IO = 0x8000;
	    *(short *)CGCR4@IO = 0x0300;
	    *(short *)CGCR3@IO = 0x0806;
	    *(short *)CGCR1@IO = 0x8262;
	}

    // wait for PLL lock
    for(i=0;i<0xff;i++);

    // Switch to PLL clk
    *(short *)CCR2@IO = 0x1;

    GEL_TextOut("PLL Init Done (40.04 MHz).\n");
}


ProgramPLL_60MHz() {
    int i;

    GEL_TextOut("Configure PLL (60.00 MHz).\n");
    // Enable clocks to all peripherals
    *(short *)PCGCR1@IO = 0x0;
    *(short *)PCGCR2@IO = 0x0;

    // bypass PLL
    *(short *)CCR2@IO = 0x0;

    // set CLR_CNTL = 0
    *(short *)CGCR1@IO = *(short *)CGCR1@IO & 0x7FFF;

	if(ClkSelSetting()) {  // CLKIN source (12MHz)
        *(short *)CGCR2@IO = 0x016E;  //RDBYPASS=0, ML=0, RDRATIO=16Eh(366)
	    *(short *)CGCR4@IO = 0x0000;
	    *(short *)CGCR3@IO = 0x0806;
	    *(short *)CGCR1@IO = 0x81CB;
	}
	else {  // RTC osc source (32.768kHz)
	    *(short *)CGCR2@IO = 0xB000;
	    *(short *)CGCR4@IO = 0x0000;
	    *(short *)CGCR3@IO = 0x0806;
	    *(short *)CGCR1@IO = 0x81CB;
    }

    // wait for PLL lock
    for(i=0;i<0xff;i++);

    // Switch to PLL clk
    *(short *)CCR2@IO = 0x1;

    GEL_TextOut("PLL Init Done (60.00 MHz).\n");
}

ProgramPLL_75MHz() {
    int i;

    GEL_TextOut("Configure PLL (75.00 MHz).\n");
    // Enable clocks to all peripherals
    *(short *)PCGCR1@IO = 0x0;
    *(short *)PCGCR2@IO = 0x0;

    // bypass PLL
    *(short *)CCR2@IO = 0x0;

	// set CLR_CNTL = 0
    *(short *)CGCR1@IO = *(short *)CGCR1@IO & 0x7FFF;

	if(ClkSelSetting()) {  // CLKIN source (12MHz)
        *(short *)CGCR2@IO = 0x016E;  //RDBYPASS=0, ML=0, RDRATIO=16Eh(366)
	    *(short *)CGCR4@IO = 0x0000;
	    *(short *)CGCR3@IO = 0x0806;
	    *(short *)CGCR1@IO = 0x823B;
	}
	else {  // RTC osc source (32.768kHz)
	    *(short *)CGCR2@IO = 0x9000;
	    *(short *)CGCR4@IO = 0x0000;
	    *(short *)CGCR3@IO = 0x0806;
	    *(short *)CGCR1@IO = 0x823B;
	}

    // wait for PLL lock
    for(i=0;i<0xff;i++);

    // Switch to PLL clk
    *(short *)CCR2@IO = 0x1;

    GEL_TextOut("PLL Init Done (75.00 MHz).\n");
}

ProgramPLL_100MHz() {
    int i;

    GEL_TextOut("Configure PLL (100.00 MHz).\n");
    // Enable clocks to all peripherals
    *(short *)PCGCR1@IO = 0x0;
    *(short *)PCGCR2@IO = 0x0;

    // bypass PLL
    *(short *)CCR2@IO = 0x0;

	// set CLR_CNTL = 0
    *(short *)CGCR1@IO = *(short *)CGCR1@IO & 0x7FFF;

	if(ClkSelSetting()) {  // CLKIN source (12MHz)
        *(short *)CGCR2@IO = 0x016E;  //RDBYPASS=0, ML=0, RDRATIO=16Eh(366)
	    *(short *)CGCR4@IO = 0x0000;
	    *(short *)CGCR3@IO = 0x0806;
	    *(short *)CGCR1@IO = 0x82FA;
    }
	else {  // RTC osc source (32.768kHz)
	    *(short *)CGCR2@IO = 0x8000;
	    *(short *)CGCR4@IO = 0x0000;
	    *(short *)CGCR3@IO = 0x0806;
	    *(short *)CGCR1@IO = 0x82FA;
    }

    // wait for PLL lock
    for(i=0;i<0xff;i++);

    // Switch to PLL clk
    *(short *)CCR2@IO = 0x1;

    GEL_TextOut("PLL Init Done (100.00 MHz).\n");
}

ClkSelSetting() {
    int i;

	i = *(short *)CCR2@IO & 0x0004;

	if(i)
	  return 1;
	else
	  return 0;
}