/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  evmam1808.gel                                                           *
 *  Version 0.02                                                            *
 *                                                                          *
 *  This GEL file is designed to be used in conjunction with                *
 *  CCStudio 3.3+ and the omap-l138 based EVM.                              *
 *                                                                          *
 *  Version History:                                                        *
 *  0.01 Initial Release                                                    *
 *  0.02 Fixed RMII Hot Menu Item                                           *
 * ------------------------------------------------------------------------ */
/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  StartUp( )                                                              *
 *      Setup Memory Map                                                    *
 *                                                                          *
 * ------------------------------------------------------------------------ */
StartUp( )
{
    Setup_Memory_Map( );
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  OnTargetConnect( )                                                      *
 *      Setup PinMux, Power, PLLs, SDRAM & EMIFs                            *
 *                                                                          *
 * ------------------------------------------------------------------------ */
OnTargetConnect( )
{
    GEL_TextOut( "\nAM1808 ARM Startup Sequence\n\n" );

    Setup_System_Config( );         // Setup Pin Mux and other system module registers
    Setup_Psc_All_On( );            // Setup All Power Domains
    Setup_PLL0();                   // Setup PLL0 (300MHZ ARM, 300MHz DSP, 133MHz EMIFs
    Setup_EMIFA();                  // Async EMIF
    Setup_PLL1();                   // PLL for DDR Clock
    DDRConfig(132);                 // Setup DDR

    GEL_TextOut( "\nStartup Complete.\n\n" );
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  OnPreFileLoaded( )                                                      *
 *      This function is called automatically when the 'Load Program'       *
 *      Menu item is selected.                                              *
 *                                                                          *
 * ------------------------------------------------------------------------ */
OnPreFileLoaded( )
{
    /*
     *  GEL_Reset() is used to deal with the worst case senario of
     *  unknown target state.  If for some reason a reset is not desired
     *  upon target connection, GEL_Reset() may be removed and replaced
     *  with something "less brutal" like a cache initialization
     *  function.
     */
    GEL_Reset( );

//    Disable_EDMA( );                // Disable EDMA

    GEL_TextOut( "\n" );
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  OnRestart( )                                                            *
 *      This function is called by CCS when you do Debug->Restart.          *
 *      The goal is to put the CPU into a known good state with respect to  *
 *      edma.                                                               *
 *      Failure to do this can cause problems when you restart and          *
 *      run your application code multiple times.  This is different        *
 *      then OnPreFileLoaded() which will do a GEL_Reset() to get the       *
 *      ARM9 into a known good state.                                       *
 *                                                                          *
 * ------------------------------------------------------------------------ */
OnRestart( int nErrorCode )
{
    Disable_EDMA( );                // Disable EDMA

    GEL_TextOut( "\n" );
}

menuitem "AM1808 Memory Map";

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_Memory_Map( )                                                     *
 *      Setup the Memory Map for DSP.                                       *
 *                                                                          *
 * ------------------------------------------------------------------------ */
hotmenu
Setup_Memory_Map( )
{
    GEL_MapOn( );
    GEL_MapReset( );

    /* DSP */
    GEL_MapAddStr( 0x00700000, 0, 0x00100000, "R|W|AS4", 0 );   // DSP L2 ROM
    GEL_MapAddStr( 0x00800000, 0, 0x00040000, "R|W|AS4", 0 );   // DSP l2 RAM
    GEL_MapAddStr( 0x00E00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1P RAM
    GEL_MapAddStr( 0x00F00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1D RAM
    GEL_MapAddStr( 0x01800000, 0, 0x00010000, "R|W|AS4", 0 );   // DSP Interrupt Controller
    GEL_MapAddStr( 0x01810000, 0, 0x00001000, "R|W|AS4", 0 );   // DSP Powerdown Controller
    GEL_MapAddStr( 0x01811000, 0, 0x00001000, "R|W|AS4", 0 );   // DSP Security ID
    GEL_MapAddStr( 0x01812000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP Revision ID
    GEL_MapAddStr( 0x01820000, 0, 0x00010000, "R|W|AS4", 0 );   // DSP EMC
    GEL_MapAddStr( 0x01830000, 0, 0x00010000, "R|W|AS4", 0 );   // DSP Internal Reserved
    GEL_MapAddStr( 0x01840000, 0, 0x00010000, "R|W|AS4", 0 );   // DSP Memory System

    GEL_MapAddStr( 0x11700000, 0, 0x00100000, "R|W|AS4", 0 );   // DSP L2 ROM (mirror)
    GEL_MapAddStr( 0x11800000, 0, 0x00040000, "R|W|AS4", 0 );   // DSP l2 RAM (mirror)
    GEL_MapAddStr( 0x11E00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1P RAM (mirror)
    GEL_MapAddStr( 0x11F00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1D RAM (mirror)

    /* Shared RAM */
    GEL_MapAddStr( 0x80000000, 0, 0x00020000, "R|W|AS4", 0 );   // On-chip RAM

    /* EMIFA */
    GEL_MapAddStr( 0x68000000, 0, 0x00008000, "R|W|AS4", 0 );   // EMIFA Control
    GEL_MapAddStr( 0x40000000, 0, 0x20000000, "R|W|AS4", 0 );   // EMIFA SDRAM Data CS0
    GEL_MapAddStr( 0x60000000, 0, 0x02000000, "R|W|AS4", 0 );   // AEMIF CS2
    GEL_MapAddStr( 0x62000000, 0, 0x02000000, "R|W|AS4", 0 );   // AEMIF CS3
    GEL_MapAddStr( 0x64000000, 0, 0x02000000, "R|W|AS4", 0 );   // AEMIF CS4
    GEL_MapAddStr( 0x66000000, 0, 0x02000000, "R|W|AS4", 0 );   // AEMIF CS5

    /* DDR */
    GEL_MapAddStr( 0xB0000000, 0, 0x00008000, "R|W|AS4", 0 );   // EMIFB Control
    GEL_MapAddStr( 0xC0000000, 0, 0x20000000, "R|W|AS4", 0 );   // EMIFB SDRAM Data

    /* Peripherals */
    GEL_MapAddStr( 0x01C00000, 0, 0x00008000, "R|W|AS4", 0 );   // EDMA3 CC
    GEL_MapAddStr( 0x01C08000, 0, 0x00000400, "R|W|AS4", 0 );   // EDMA3 TC0
    GEL_MapAddStr( 0x01C08400, 0, 0x00000400, "R|W|AS4", 0 );   // EDMA3 TC1
    GEL_MapAddStr( 0x01C10000, 0, 0x00001000, "R|W|AS4", 0 );   // PSC 0
    GEL_MapAddStr( 0x01C11000, 0, 0x00001000, "R|W|AS4", 0 );   // PLL Controller 0
    GEL_MapAddStr( 0x01C14000, 0, 0x00001000, "R|W|AS4", 0 );   // SYSCFG0
    GEL_MapAddStr( 0x01C20000, 0, 0x00001000, "R|W|AS4", 0 );   // Timer 0
    GEL_MapAddStr( 0x01C21000, 0, 0x00001000, "R|W|AS4", 0 );   // Timer 1
    GEL_MapAddStr( 0x01C22000, 0, 0x00001000, "R|W|AS4", 0 );   // I2C 0
    GEL_MapAddStr( 0x01C23000, 0, 0x00001000, "R|W|AS4", 0 );   // RTC
    GEL_MapAddStr( 0x01C40000, 0, 0x00001000, "R|W|AS4", 0 );   // MMC/SD 0
    GEL_MapAddStr( 0x01C41000, 0, 0x00001000, "R|W|AS4", 0 );   // SPI 0
    GEL_MapAddStr( 0x01C42000, 0, 0x00001000, "R|W|AS4", 0 );   // UART 0
    GEL_MapAddStr( 0x01D00000, 0, 0x00001000, "R|W|AS4", 0 );   // McASP 0 Control
    GEL_MapAddStr( 0x01D01000, 0, 0x00001000, "R|W|AS4", 0 );   // McASP 0 FIFO Ctrl
    GEL_MapAddStr( 0x01D02000, 0, 0x00001000, "R|W|AS4", 0 );   // McASP 0 Data
    GEL_MapAddStr( 0x01D04000, 0, 0x00001000, "R|W|AS4", 0 );   // McASP 1 Control
    GEL_MapAddStr( 0x01D05000, 0, 0x00001000, "R|W|AS4", 0 );   // McASP 1 FIFO Ctrl
    GEL_MapAddStr( 0x01D06000, 0, 0x00001000, "R|W|AS4", 0 );   // McASP 1 Data
    GEL_MapAddStr( 0x01D0C000, 0, 0x00001000, "R|W|AS4", 0 );   // UART 1
    GEL_MapAddStr( 0x01D0D000, 0, 0x00001000, "R|W|AS4", 0 );   // UART 2
    GEL_MapAddStr( 0x01D10000, 0, 0x00000800, "R|W|AS4", 0 );   // McBSP0
    GEL_MapAddStr( 0x01D10800, 0, 0x00000800, "R|W|AS4", 0 );   // McBSP0 FIFO Ctrl
    GEL_MapAddStr( 0x01D11000, 0, 0x00000800, "R|W|AS4", 0 );   // McBSP1
    GEL_MapAddStr( 0x01D11800, 0, 0x00000800, "R|W|AS4", 0 );   // McBSP1 FIFO Ctrl
    GEL_MapAddStr( 0x01E00000, 0, 0x00010000, "R|W|AS4", 0 );   // USB0
    GEL_MapAddStr( 0x01E10000, 0, 0x00001000, "R|W|AS4", 0 );   // UHPI
    GEL_MapAddStr( 0x01E13000, 0, 0x00001000, "R|W|AS4", 0 );   // LCD Controller
    GEL_MapAddStr( 0x01E14000, 0, 0x00001000, "R|W|AS4", 0 );   // MPU 1
    GEL_MapAddStr( 0x01E15000, 0, 0x00001000, "R|W|AS4", 0 );   // MPU 2
    GEL_MapAddStr( 0x01E16000, 0, 0x00001000, "R|W|AS4", 0 );   // UPP
	GEL_MapAddStr( 0x01E17000, 0, 0x00001000, "R|W|AS4", 0 );   // VPIF
    GEL_MapAddStr( 0x01E18000, 0, 0x00002000, "R|W|AS4", 0 );   // SATA
    GEL_MapAddStr( 0x01E1A000, 0, 0x00001000, "R|W|AS4", 0 );   // PLL Controller 1
    GEL_MapAddStr( 0x01E1B000, 0, 0x00001000, "R|W|AS4", 0 );   // MMCSD1
    GEL_MapAddStr( 0x01E20000, 0, 0x00002000, "R|W|AS4", 0 );   // EMAC Control Module RAM
    GEL_MapAddStr( 0x01E22000, 0, 0x00001000, "R|W|AS4", 0 );   // EMAC Control Module Registers
    GEL_MapAddStr( 0x01E23000, 0, 0x00001000, "R|W|AS4", 0 );   // EMAC Control Registers
    GEL_MapAddStr( 0x01E24000, 0, 0x00001000, "R|W|AS4", 0 );   // EMAC MDIO port
    GEL_MapAddStr( 0x01E25000, 0, 0x00001000, "R|W|AS4", 0 );   // USB1
    GEL_MapAddStr( 0x01E26000, 0, 0x00001000, "R|W|AS4", 0 );   // GPIO
    GEL_MapAddStr( 0x01E27000, 0, 0x00001000, "R|W|AS4", 0 );   // PSC 1
    GEL_MapAddStr( 0x01E28000, 0, 0x00001000, "R|W|AS4", 0 );   // I2C 1
    GEL_MapAddStr( 0x01E2C000, 0, 0x00001000, "R|W|AS4", 0 );   // System Config 1
    GEL_MapAddStr( 0x01E30000, 0, 0x00008000, "R|W|AS4", 0 );   // EDMA3 CC1
    GEL_MapAddStr( 0x01E38000, 0, 0x00000400, "R|W|AS4", 0 );   // EDMA3 TC2
    GEL_MapAddStr( 0x01F00000, 0, 0x00001000, "R|W|AS4", 0 );   // eHRPWM 0
    GEL_MapAddStr( 0x01F01000, 0, 0x00001000, "R|W|AS4", 0 );   // HRPWM 0
    GEL_MapAddStr( 0x01F02000, 0, 0x00001000, "R|W|AS4", 0 );   // eHRPWM 1
    GEL_MapAddStr( 0x01F03000, 0, 0x00001000, "R|W|AS4", 0 );   // HRPWM 1
    GEL_MapAddStr( 0x01F06000, 0, 0x00001000, "R|W|AS4", 0 );   // ECAP 0
    GEL_MapAddStr( 0x01F07000, 0, 0x00001000, "R|W|AS4", 0 );   // ECAP 1
    GEL_MapAddStr( 0x01F08000, 0, 0x00001000, "R|W|AS4", 0 );   // ECAP 2
    GEL_MapAddStr( 0x01F0C000, 0, 0x00001000, "R|W|AS4", 0 );   // Timer2
    GEL_MapAddStr( 0x01F0D000, 0, 0x00001000, "R|W|AS4", 0 );   // Timer3
    GEL_MapAddStr( 0x01F0E000, 0, 0x00001000, "R|W|AS4", 0 );   // SPI1
    GEL_MapAddStr( 0x01F10000, 0, 0x00001000, "R|W|AS4", 0 );   // McBSP0 FIFO Data
    GEL_MapAddStr( 0x01F11000, 0, 0x00001000, "R|W|AS4", 0 );   // McBSP1 FIFO Data
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Clear_Memory_Map( )                                                     *
 *      Clear the Memory Map                                                *
 *                                                                          *
 * ------------------------------------------------------------------------ */
hotmenu
Clear_Memory_Map( )
{
    GEL_MapOff( );
    GEL_MapReset( );
}

menuitem "EVMAM1808 Functions";

_wait( int delay )
{
    int i;
    for( i = 0 ; i < delay ; i++ ){}
}

#define SYS_BASE            0x01C14000
#define REVID               *(unsigned int*)(SYS_BASE + 0x000)  
#define DIEIDR0             *(unsigned int*)(SYS_BASE + 0x008)
#define DIEIDR1             *(unsigned int*)(SYS_BASE + 0x00C)
#define DIEIDR2             *(unsigned int*)(SYS_BASE + 0x010)
#define DIEIDR3             *(unsigned int*)(SYS_BASE + 0x014)
#define DEVIDR0             *(unsigned int*)(SYS_BASE + 0x018)
#define BOOTCFG             *(unsigned int*)(SYS_BASE + 0x020)
#define KICK0R              *(unsigned int*)(SYS_BASE + 0x038)  
#define KICK1R              *(unsigned int*)(SYS_BASE + 0x03c)  
#define HOST0CFG            *(unsigned int*)(SYS_BASE + 0x040)
#define IRAWSTAT            *(unsigned int*)(SYS_BASE + 0x0E0)  
#define IENSTAT             *(unsigned int*)(SYS_BASE + 0x0E4)  
#define IENSET              *(unsigned int*)(SYS_BASE + 0x0E8)  
#define IENCLR              *(unsigned int*)(SYS_BASE + 0x0EC)  
#define EOI                 *(unsigned int*)(SYS_BASE + 0x0F0)  
#define FLTADDRR            *(unsigned int*)(SYS_BASE + 0x0F4)  
#define FLTSTAT             *(unsigned int*)(SYS_BASE + 0x0F8)  
#define MSTPRI0             *(unsigned int*)(SYS_BASE + 0x110)  
#define MSTPRI1             *(unsigned int*)(SYS_BASE + 0x114)  
#define MSTPRI2             *(unsigned int*)(SYS_BASE + 0x118) 
#define PINMUX0             *(unsigned int*)(SYS_BASE + 0x120)  //PINMUX0
#define PINMUX1             *(unsigned int*)(SYS_BASE + 0x124)  //PINMUX1
#define PINMUX2             *(unsigned int*)(SYS_BASE + 0x128)  //PINMUX2
#define PINMUX3             *(unsigned int*)(SYS_BASE + 0x12C)  //PINMUX3
#define PINMUX4             *(unsigned int*)(SYS_BASE + 0x130)  //PINMUX4
#define PINMUX5             *(unsigned int*)(SYS_BASE + 0x134)  //PINMUX5
#define PINMUX6             *(unsigned int*)(SYS_BASE + 0x138)  //PINMUX6
#define PINMUX7             *(unsigned int*)(SYS_BASE + 0x13C)  //PINMUX7
#define PINMUX8             *(unsigned int*)(SYS_BASE + 0x140)  //PINMUX8
#define PINMUX9             *(unsigned int*)(SYS_BASE + 0x144)  //PINMUX9
#define PINMUX10            *(unsigned int*)(SYS_BASE + 0x148)  //PINMUX10
#define PINMUX11            *(unsigned int*)(SYS_BASE + 0x14C)  //PINMUX11
#define PINMUX12            *(unsigned int*)(SYS_BASE + 0x150)  //PINMUX12
#define PINMUX13            *(unsigned int*)(SYS_BASE + 0x154)  //PINMUX13
#define PINMUX14            *(unsigned int*)(SYS_BASE + 0x158)  //PINMUX14
#define PINMUX15            *(unsigned int*)(SYS_BASE + 0x15C)  //PINMUX15
#define PINMUX16            *(unsigned int*)(SYS_BASE + 0x160)  //PINMUX16
#define PINMUX17            *(unsigned int*)(SYS_BASE + 0x164)  //PINMUX17
#define PINMUX18            *(unsigned int*)(SYS_BASE + 0x168)  //PINMUX18
#define PINMUX19            *(unsigned int*)(SYS_BASE + 0x16C)  //PINMUX19
#define SUSPSRC             *(unsigned int*)(SYS_BASE + 0x170) 
#define CHIPSIG             *(unsigned int*)(SYS_BASE + 0x174) 
#define CHIPSIG_CLR         *(unsigned int*)(SYS_BASE + 0x178) 
#define CFGCHIP0            *(unsigned int*)(SYS_BASE + 0x17C) 
#define CFGCHIP1            *(unsigned int*)(SYS_BASE + 0x180) 
#define CFGCHIP2            *(unsigned int*)(SYS_BASE + 0x184) 
#define CFGCHIP3            *(unsigned int*)(SYS_BASE + 0x188) 
#define CFGCHIP4            *(unsigned int*)(SYS_BASE + 0x18C) 

#define PLL0_BASE       0x01C11000                              // SYSTEM PLL BASE ADDRESS
#define PLL0_PID        *(unsigned int*) (PLL0_BASE + 0x00)     // PID
#define PLL0_RSTYPE     *(unsigned int*) (PLL0_BASE + 0xE4)     // Reset Type status Reg
#define PLL0_PLLCTL     *(unsigned int*) (PLL0_BASE + 0x100)    // PLL Control Register
#define PLL0_OCSEL      *(unsigned int*) (PLL0_BASE + 0x104)    // OBSCLK Select Register
#define PLL0_PLLM       *(unsigned int*) (PLL0_BASE + 0x110)    // PLL Multiplier 
#define PLL0_PREDIV     *(unsigned int*) (PLL0_BASE + 0x114)    // Pre divider
#define PLL0_PLLDIV1    *(unsigned int*) (PLL0_BASE + 0x118)    // Diveder-1  
#define PLL0_PLLDIV2    *(unsigned int*) (PLL0_BASE + 0x11C)    // Diveder-2
#define PLL0_PLLDIV3    *(unsigned int*) (PLL0_BASE + 0x120)    // Diveder-3  
#define PLL0_OSCDIV1    *(unsigned int*) (PLL0_BASE + 0x124)    // Oscilator Divider  
#define PLL0_POSTDIV    *(unsigned int*) (PLL0_BASE + 0x128)    // Post Divider  
#define PLL0_PLLCMD     *(unsigned int*) (PLL0_BASE + 0x138)    // Command Reg
#define PLL0_PLLSTAT    *(unsigned int*) (PLL0_BASE + 0x13C)    // Status Reg
#define PLL0_ALNCTL     *(unsigned int*) (PLL0_BASE + 0x140)    // Clock Align Control Reg
#define PLL0_DCHANGE    *(unsigned int*) (PLL0_BASE + 0x144)    // PLLDIV Ratio Chnage status
#define PLL0_CKEN       *(unsigned int*) (PLL0_BASE + 0x148)    // Clock Enable Reg
#define PLL0_CKSTAT     *(unsigned int*) (PLL0_BASE + 0x14C)    // Clock Status Reg
#define PLL0_SYSTAT     *(unsigned int*) (PLL0_BASE + 0x150)    // Sysclk status reg
#define PLL0_PLLDIV4    *(unsigned int*) (PLL0_BASE + 0x160)    // Divider 4
#define PLL0_PLLDIV5    *(unsigned int*) (PLL0_BASE + 0x164)    // Divider 5
#define PLL0_PLLDIV6    *(unsigned int*) (PLL0_BASE + 0x168)    // Divider 6
#define PLL0_PLLDIV7    *(unsigned int*) (PLL0_BASE + 0x16C)    // Divider 7
#define PLL0_EMUCNT0    *(unsigned int*) (PLL0_BASE + 0x1F0)    // EMUCNT0
#define PLL0_EMUCNT1    *(unsigned int*) (PLL0_BASE + 0x1F4)    // EMUCNT1
#define PLLEN_MUX_SWITCH  4 
#define PLL_LOCK_TIME_CNT 2400

#define PLL1_BASE       0x01E1A000                              // SYSTEM PLL1 BASE ADDRESS
#define PLL1_PID        *(unsigned int*) (PLL1_BASE + 0x00)     /*PID*/
#define PLL1_PLLCTL     *(unsigned int*) (PLL1_BASE + 0x100)    /*PLL Control Register*/
#define PLL1_OCSEL      *(unsigned int*) (PLL1_BASE + 0x104)    /*OBSCLK Select Register*/
#define PLL1_PLLM       *(unsigned int*) (PLL1_BASE + 0x110)    /*PLL Multiplier*/
#define PLL1_PREDIV     *(unsigned int*) (PLL1_BASE + 0x114)    /*Pre divider*/
#define PLL1_PLLDIV1    *(unsigned int*) (PLL1_BASE + 0x118)    /*Divider-1*/
#define PLL1_PLLDIV2    *(unsigned int*) (PLL1_BASE + 0x11C)    /*Divider-2*/
#define PLL1_PLLDIV3    *(unsigned int*) (PLL1_BASE + 0x120)    /*Divider-3*/
#define PLL1_OSCDIV1    *(unsigned int*) (PLL1_BASE + 0x124)    /*Oscilator Divider*/
#define PLL1_POSTDIV    *(unsigned int*) (PLL1_BASE + 0x128)    /*Post Divider*/
#define PLL1_PLLCMD     *(unsigned int*) (PLL1_BASE + 0x138)    /*Command Reg*/
#define PLL1_PLLSTAT    *(unsigned int*) (PLL1_BASE + 0x13C)    /*Status Reg*/
#define PLL1_ALNCTL     *(unsigned int*) (PLL1_BASE + 0x140)    /*Clock Align Control Reg*/
#define PLL1_DCHANGE    *(unsigned int*) (PLL1_BASE + 0x144)    /*PLLDIV Ratio Chnage status*/
#define PLL1_SYSTAT     *(unsigned int*) (PLL1_BASE + 0x150)    /*Sysclk status reg*/
#define PLL1_EMUCNT0    *(unsigned int*) (PLL1_BASE + 0x1F0)    /*EMUCNT0*/
#define PLL1_EMUCNT1    *(unsigned int*) (PLL1_BASE + 0x1F4)    /*EMUCNT1*/

#define PLL_STABILIZATION_TIME   2000
#define PLL_RESET_TIME_CNT       200

/*PSC Module Related Registers*/              
#define PSC0_BASE       0x01C10000
#define PSC1_BASE       0x01E27000

#define PSC0_MDCTL      (PSC0_BASE+0xA00)
#define PSC0_MDSTAT     (PSC0_BASE+0x800)
#define PSC0_PTCMD      *(unsigned int*) (PSC0_BASE + 0x120)
#define PSC0_PTSTAT     *(unsigned int*) (PSC0_BASE + 0x128)

#define PSC1_MDCTL      (PSC1_BASE+0xA00)
#define PSC1_MDSTAT     (PSC1_BASE+0x800)
#define PSC1_PTCMD      *(unsigned int*) (PSC1_BASE + 0x120)
#define PSC1_PTSTAT     *(unsigned int*) (PSC1_BASE + 0x128)


/*Enable Function for PSC0*/
PSC0_lPSC_enable(unsigned int PD, unsigned int LPSC_num) {

  *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
  PSC0_PTCMD = 0x1<<PD;
  while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) ; /*Wait for power state transition to finish*/
  while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3);
}

/*Force module state without handshaking */
PSC1_LPSC_force(unsigned int LPSC_num) {
    *(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) | 0x80000000);
}

/*Enable Function for PSC1*/
PSC1_lPSC_enable(unsigned int PD, unsigned int LPSC_num) {

  *(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
  PSC1_PTCMD = 0x1<<PD;
  while( (PSC1_PTSTAT & (0x1<<PD) ) !=0) ; //Wait for power state transition to finish
  while( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3);
}
/*Enable Function for PSC1*/
PSC1_LPSC_enable(unsigned int PD, unsigned int LPSC_num) {
    if( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) != 0x3 ) {
      *(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
      PSC1_PTCMD = 0x1<<PD;

      /*Wait for power state transition to finish*/
      while( (PSC1_PTSTAT & (0x1<<PD) ) !=0) ;

      while( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3);
    }
}

/*SyncReset Function for PSC1*/
PSC1_LPSC_SyncReset(unsigned int PD, unsigned int LPSC_num) {
    if( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) != 0x1 ) {
      *(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0001;
      PSC1_PTCMD = 0x1<<PD;

      /*Wait for power state transition to finish*/
      while( (PSC1_PTSTAT & (0x1<<PD) ) !=0) ;

      while( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) !=0x1);
    }
}


/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Disable_IRQ_Flush_Cache( )                                              *
 *      Flush Cache & Disable Interrupts                                           *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Disable_IRQ_Flush_Cache( )
{

}


/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Disable_EDMA( )                                                         *
 *      Disabe EDMA events and interrupts, clear any pending events         *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Disable_EDMA( )
{
    #define EDMA_3CC_IECRH          *( unsigned int* )( 0x01c0105c )
    #define EDMA_3CC_EECRH          *( unsigned int* )( 0x01c0102c )
    #define EDMA_3CC_ICRH           *( unsigned int* )( 0x01c01074 )
    #define EDMA_3CC_ECRH           *( unsigned int* )( 0x01c0100c )

    #define EDMA_3CC_IECR           *( unsigned int* )( 0x01c01058 )
    #define EDMA_3CC_EECR           *( unsigned int* )( 0x01c01028 )
    #define EDMA_3CC_ICR            *( unsigned int* )( 0x01c01070 )
    #define EDMA_3CC_ECR            *( unsigned int* )( 0x01c01008 )

    GEL_TextOut( "Disable EDMA events\n" );

    EDMA_3CC_IECRH  = 0xffffffff;   // IERH - Disable high interrupts
    EDMA_3CC_EECRH  = 0xffffffff;   // EERH - Disable high events
    EDMA_3CC_ICRH   = 0xffffffff;   // ICRH - Clear high interrupts
    EDMA_3CC_ECRH   = 0xffffffff;   // ICRH - Clear high events

    EDMA_3CC_IECR   = 0xffffffff;   // IER  - Disable low interrupts
    EDMA_3CC_EECR   = 0xffffffff;   // EER  - Disable low events
    EDMA_3CC_ICR    = 0xffffffff;   // ICR  - Clear low interrupts
    EDMA_3CC_ECR    = 0xffffffff;   // ICRH - Clear low events
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Enable_Instruction_Cache( )                                             *
 *      Enable I-Cache                                                      *
 *                                                                          *
 * ------------------------------------------------------------------------ */
hotmenu Enable_Instruction_Cache( )
{
    GEL_TextOut( "\Enable Instruction Cache.\n\n" );

    CPSR = 0x400000d3;              // Set to supervisor mode, disable IRQ/FIQ
    REG_CP15_I_CACHE = 1;           // Enable Instruction Cache
} 

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_System_Config( )                                                  *
 *      Configure PINMUX and other system module registers                  *
 *                                                                          *
 * ------------------------------------------------------------------------ */
hotmenu
Setup_System_Config( )
{

    GEL_TextOut( "Setup PINMUX Registers... " );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock)

    PINMUX4  = 0x00002288;  // I2C0, MDIO
    /* Ethernet Pinmux */
/*    PINMUX2  = 0x88888880;  // MII
    PINMUX3  = 0x88888888;  // MII
    CFGCHIP3 &= ~0x00000100; // MII

    //PINMUX6  = 0x00000080;   // MII MDIO enable (BUFF_ENn)
    //PINMUX14 = 0x88888800;  // RMII  
    //PINMUX15 = 0x00000080;  // RMII
    //CFGCHIP2 |= 0x00000100; // RMII
*/
    /* LCD Pinmux */
 /*   PINMUX16  = 0x22222200;  // LCDIO
    PINMUX17  = 0x22222222;  // LCDIO
    PINMUX18  = 0x00000022;  // LCDIO
    PINMUX18 |= 0x22000000;  // LCD_MCLK, LCD_PCLK 
    PINMUX19  = 0x02000022;  // LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC
    PINMUX5   = 0x00000008;  // GP2[15]
    PINMUX5  |= 0x80000000;  // GP2[8]
    PINMUX6   = 0x00000080;  // BUFF_ENn*/

    /* UART PINMUX */
    /*PINMUX0 = 0x44000000;
    PINMUX4 = 0x00220000;*/

    /* SD0 PINMUX */
    /*PINMUX10 = 0x22222222;
    PINMUX11 = 0x00000022;*/

    /* SPI ROM PINMUX */
    /*PINMUX5   = 0x00111110;  // SPI pins
    PINMUX6   = 0x00000080;  // BUFF_ENn*/

    /* MCASP PINMUX */
    /*PINMUX0 = 0x00111111;
    PINMUX1 = 0x00011000;*/

    CFGCHIP2 |= 0x00001000; // Enable USB1 clock



    GEL_TextOut( "[Done]\n" );
}

hotmenu
Setup_EMIFA_PinMux()
{
    PINMUX13 &= 0x00FFFFFF;
    PINMUX13 |= 0x11000000;
    PINMUX14  = 0x11111111;
    PINMUX15  = 0x11111111;
    PINMUX16  = 0x11111111;
    PINMUX17  = 0x11111111;
    PINMUX18  = 0x11111111;
    PINMUX19 &= 0xFFFFFFF0;
    PINMUX19 |= 0x00000001;

    GEL_TextOut( "[Done]\n" );
}

/*Enable Function for PSC0*/
PSC0_lPSC_enableARM(unsigned int PD, unsigned int LPSC_num) {

  *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFEE0) | 0x0103;

  PSC0_PTCMD = 0x1<<PD;
  while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) ; /*Wait for power state transition to finish*/
  while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3);
}

hotmenu Enable_ARM()
{
    /* Turn on ARM RAM */
    PSC0_lPSC_enable(0, 7);

    /* Put branch to self at ARM vector table before releasing PSC */
    *( unsigned int* )( 0xFFFF0000 ) = 0xEAFFFFFE;
    *( unsigned int* )( 0xFFFF0004 ) = 0xEAFFFFFE;
    *( unsigned int* )( 0xFFFF0008 ) = 0xEAFFFFFE;
    *( unsigned int* )( 0xFFFF000C ) = 0xEAFFFFFE;

    HOST0CFG = 0x00000001; 

    /* Turn on ARM */
    PSC0_lPSC_enableARM(0, 14);

    GEL_TextOut(" ARM Enabled\n");
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_Psc_All_On( )                                                     *
 *      Enable all PSC modules on ALWAYSON and DSP power dominas.           *
 *                                                                          *
 * ------------------------------------------------------------------------ */
hotmenu
Setup_Psc_All_On( )
{
    int i;
    GEL_TextOut( "Setup Power Modules (All on)... " );

    // PSC0
    PSC0_lPSC_enable(0, 0);   // EDMA_CC0
    PSC0_lPSC_enable(0, 1);   // EDMA_TC0
    PSC0_lPSC_enable(0, 2);   // EDMA_TC1
    PSC0_lPSC_enable(0, 3);   // EMIFA
    PSC0_lPSC_enable(0, 4);   // SPI0
    PSC0_lPSC_enable(0, 5);   // MMCSD0
    PSC0_lPSC_enable(0, 6);   // ARM_AINTC
    PSC0_lPSC_enable(0, 7);   // ARM_RAMROM
    // #8 not used
    PSC0_lPSC_enable(0, 9);   // UART0
    PSC0_lPSC_enable(0, 10);  // SCR0
    PSC0_lPSC_enable(0, 11);  // SCR1
    PSC0_lPSC_enable(0, 12);  // SCR2
    // #13 not used
//    PSC0_lPSC_enable(0, 14);  // ARM

    // PSC1
    PSC1_lPSC_enable(0, 0);   // EDMA_CC1
    PSC1_lPSC_enable(0, 1);   // USB20
    PSC1_lPSC_enable(0, 2);   // USB11
    PSC1_lPSC_enable(0, 3);   // GPIO
    PSC1_lPSC_enable(0, 4);   // UHPI
    PSC1_lPSC_enable(0, 5);   // EMAC
    PSC1_lPSC_enable(0, 6);   // DDR
    PSC1_lPSC_enable(0, 7);   // MCASP0
        PSC1_LPSC_force(8);
    PSC1_lPSC_enable(0, 8);   // SATA

    PSC1_lPSC_enable(0, 9);   // VPIF
    PSC1_lPSC_enable(0, 10);  // SPI1
    PSC1_lPSC_enable(0, 11);  // I2C1
    PSC1_lPSC_enable(0, 12);  // UART1
    PSC1_lPSC_enable(0, 13);  // UART2
    PSC1_lPSC_enable(0, 14);  // MCBSP0
    PSC1_lPSC_enable(0, 15);  // MCBSP1
    PSC1_lPSC_enable(0, 16);  // LCDC
    PSC1_lPSC_enable(0, 17);  // EPWM
    PSC1_lPSC_enable(0, 18);  // MMCSD1
    PSC1_lPSC_enable(0, 19);  // UPP
    PSC1_lPSC_enable(0, 20);  // ECAP
    PSC1_lPSC_enable(0, 21);  // EDMA_TC2
    // #22 & 23 not used
    PSC1_lPSC_enable(0, 24);  // SCR_F0
    PSC1_lPSC_enable(0, 25);  // SCR_F1
    PSC1_lPSC_enable(0, 26);  // SCR_F2
    PSC1_lPSC_enable(0, 27);  // SCR_F6
    PSC1_lPSC_enable(0, 28);  // SCR_F7
    PSC1_lPSC_enable(0, 29);  // SCR_F8
    PSC1_lPSC_enable(0, 30);  // BR_F7
    PSC1_lPSC_enable(0, 3);  // SHARED_RAM

    GEL_TextOut( "[Done]\n" );
}


/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_EMIFA( )                                                          *
 *      Setup Async-EMIF to the specified timings using either NAND Hw      *
 *      controller or normal EMIF controller                                *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define AEMIF_AWCCR             *( unsigned int* )( 0x68000004 )
#define AEMIF_A1CR              *( unsigned int* )( 0x68000010 )
#define AEMIF_A2CR              *( unsigned int* )( 0x68000014 )
#define AEMIF_A3CR              *( unsigned int* )( 0x68000018 )
#define AEMIF_A4CR              *( unsigned int* )( 0x6800001C )
#define AEMIF_NANDFCR           *( unsigned int* )( 0x68000060 )

Setup_EMIFA( )
{
    /* Use extended wait cycles to keep CE low during NAND access */
    AEMIF_AWCCR = 0xff;

    /* Setup CS2 - 8-bit normal async */
    AEMIF_A1CR = 0x00300608;
    AEMIF_NANDFCR &= ~1;

    /* Setup CS3 - 8-bit NAND */
    AEMIF_A2CR = 0x00300388;
    AEMIF_NANDFCR |= 2;

    /* Setup CS4 - 8-bit normal async */
    AEMIF_A3CR = 0x00a00504;  // Setup=0, Strobe=A, Hold=0, TA=1, 8-bit
    AEMIF_NANDFCR &= ~4;

    /* Setup CS5 - 8-bit normal async */
    AEMIF_A4CR = 0x00a00504;  // Setup=0, Strobe=A, Hold=0, TA=1, 8-bit
    AEMIF_NANDFCR &= ~8;
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_PLL0()                                                            *
 *      Setup PLL0                                                          *
 *                                                                          *
 * ------------------------------------------------------------------------ */
hotmenu
Setup_PLL0()
{
    int i = 0;

    /* Configure ARM, DSP at 300MHz, EMIFs at 133MHz */
    unsigned int DIV45_EN = 1;
    unsigned int CLKMODE = 0;
    unsigned int PLLM = 24;
    unsigned int POSTDIV = 1;
    unsigned int PLLDIV3 = 2;
    unsigned int PLLDIV7 = 7;

    // Moved step 2c and 2d to step 0
   /*Set PLLEN=0 and PLLRST=0, Reset the PLL*/
    PLL0_PLLCTL &=  0xFFFFFFFE;     /*PLL BYPASS MODE*/
   
   /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
   for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}   /*Make PLLEN_MUX_SWITCH as bootpacket*/

   /*Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
    PLL0_PLLCTL &= 0xFFFFFEFF;  
    PLL0_PLLCTL |= (CLKMODE<<8);  /* Make CLKSRC as BootPacket to pass the value*/

   /*Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR*/
    PLL0_PLLCTL &=  0xFFFFFFDF; 
   
   /*PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Primus*/
    PLL0_PLLCTL &=  0xFFFFFDFF;

   /* Clear PLLRST bit to 0 -Reset the PLL */
   PLL0_PLLCTL &= 0xFFFFFFF7;   
  
   /*Disable the PLL output*/ 
   PLL0_PLLCTL |= 0x10;         
   
   /*PLL initialization sequence*/
   
   /*Power up the PLL- PWRDN bit set to 0 to bring the PLL out of power down bit*/
   PLL0_PLLCTL &= 0xFFFFFFFD;
   
   /*Enable the PLL from Disable Mode PLLDIS bit to 0 - This is step is not required for Primus*/
   PLL0_PLLCTL &= 0xFFFFFFEF;
   
   /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
  /* for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}  /* Make PLL_STABILIZATION_TIME as bootpacket*/
   
   /*Program the required multiplier value in PLLM*/
   PLL0_PLLM    = PLLM; /* Make PLLMULTIPLEIR as bootpacket*/

   /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
   PLL0_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/

   /*If Necessary program the PLLDIVx*/
   /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
   while(PLL0_PLLSTAT & 0x1==1){}

   /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
    PLL0_PLLDIV3 = 0x8000 | PLLDIV3; /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/
    PLL0_PLLDIV7 = 0x8000 | PLLDIV7; /* Make PLLDIV7 as bootpacket, do it for other PLLDIVx to if required*/

    /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
    PLL0_PLLCMD |= 0x1;

    /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
    while(PLL0_PLLSTAT & 0x1==1) { } 
   
 
   /*Wait for PLL to reset properly. See PLL spec for PLL reset time - This step is not required here -step11*/
  /* for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}   /*128 MXI Cycles*/ /*Make PLL_RESET_TIME_CNT as boot packet*/
      
   /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
   PLL0_PLLCTL |= 0x8;
   
   /*Wait for PLL to lock. See PLL spec for PLL lock time*/
   for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;} /*Make PLL_LOCK_TIME_CNT as boot Packet*/ 
   
   /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
   PLL0_PLLCTL |=  0x1;

   KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
   KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock)
   CFGCHIP3 |= 0x4;       // Enable 4.5 divider PLL
   CFGCHIP3 |= 0x1;       // Select 4.5 divider for EMIFB clock source only (not EMIFA)

   GEL_TextOut( "PLL0 Setup Complete\n" );
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_PLL1( )                                                           *
 *      Setup PLL1 for DDR Clock                                            *
 *                                                                          *
 * ------------------------------------------------------------------------ */

Setup_PLL1( ) 
{
   unsigned int PLLM    = 21;
   unsigned int POSTDIV =  1;
   unsigned int PLLDIV1 =  0;
   unsigned int PLLDIV2 =  1;
   unsigned int PLLDIV3 =  2;
   unsigned int i=0;

   /* Clear PLL lock bit */
   CFGCHIP3 &= ~(0x00000020);

   /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
   PLL1_PLLCTL &= ~(0x00000020);

   /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
   PLL1_PLLCTL &= ~(0x00000200);

   /* Set PLLEN=0 to put in bypass mode*/
   PLL1_PLLCTL &= ~(0x00000001);

   /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
   for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

   /* Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
   /* PLL1_PLLCTL &= 0xFFFFFEFF;
   PLL1_PLLCTL |= (CLKMODE << 8); */

   /*Clear PLLRST bit to reset the PLL */
   PLL1_PLLCTL &= ~(0x00000008);

   /* Disable the PLL output*/
   PLL1_PLLCTL |= (0x00000010);

   /* PLL initialization sequence
   Power up the PLL by setting PWRDN bit set to 0 */
   PLL1_PLLCTL &= ~(0x00000002);

   /* Enable the PLL output*/
   PLL1_PLLCTL &= ~(0x00000010);

   /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
   for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

   /*Program the required multiplier value in PLLM*/
   PLL1_PLLM    = PLLM; /* Make PLLMULTIPLEIR as bootpacket*/

   /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
   PLL1_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/

   /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
   while(PLL1_PLLSTAT & 0x1==1){}

   /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
   PLL1_PLLDIV1 = 0x8000 | PLLDIV1;   /* Make PLLDIV1 as bootpacket, do it for other PLLDIVx to if required*/
   PLL1_PLLDIV2 = 0x8000 | PLLDIV2;   /* Make PLLDIV2 as bootpacket, do it for other PLLDIVx to if required*/
   PLL1_PLLDIV3 = 0x8000 | PLLDIV3;   /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/

   /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
   PLL1_PLLCMD |= 0x1;

   /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
   while(PLL1_PLLSTAT & 0x1==1) { }

   /*Wait for PLL to reset properly. See PLL spec for PLL reset time - */
   for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}   /*128 MXI Cycles*/

   /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
   PLL1_PLLCTL |= 0x8;

   /*Wait for PLL to lock. See PLL spec for PLL lock time*/
   for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;} /*Make PLL_LOCK_TIME_CNT as boot Packet*/

   /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
   PLL1_PLLCTL |=  0x1;

   /* SET PLL lock bit*/
   CFGCHIP3 |= (0x1 << 5) & 0x00000020;

   GEL_TextOut("PLL1 init done for DDR:132MHz\n");
}

/* DDR Registers */

#define DDRCTL_BASE        0xB0000000
#define DDRCTL_REVID       *(unsigned int*)(DDRCTL_BASE + 0x00)      // Revision ID Register
#define DDRCTL_SDRSTAT     *(unsigned int*)(DDRCTL_BASE + 0x04)      // SDRAM Status Register
#define DDRCTL_SDCR        *(unsigned int*)(DDRCTL_BASE + 0x08)      // SDRAM Configuration Register
#define DDRCTL_SDRCR       *(unsigned int*)(DDRCTL_BASE + 0x0C)      // SDRAM Refresh Control Register
#define DDRCTL_SDTIMR1     *(unsigned int*)(DDRCTL_BASE + 0x10)      // SDRAM Timing Register 1
#define DDRCTL_SDTIMR2     *(unsigned int*)(DDRCTL_BASE + 0x14)      // SDRAM Timing Register 2
#define DDRCTL_SDCR2       *(unsigned int*)(DDRCTL_BASE + 0x1C)      // SDRAM Configuration Register 2
#define DDRCTL_PBBPR       *(unsigned int*)(DDRCTL_BASE + 0x20)      // Peripheral Bus Burst Priority Register
#define DDRCTL_IRR         *(unsigned int*)(DDRCTL_BASE + 0xC0)      // Interrupt Raw Register
#define DDRCTL_IMR         *(unsigned int*)(DDRCTL_BASE + 0xC4)      // Interrupt Masked Register
#define DDRCTL_IMSR        *(unsigned int*)(DDRCTL_BASE + 0xC8)      // Interrupt Mask Set Register
#define DDRCTL_IMCR        *(unsigned int*)(DDRCTL_BASE + 0xCC)      // Interrupt Mask Clear Register
#define DDRCTL_PHYCTL      *(unsigned int*)(DDRCTL_BASE + 0xE4)      // DDR PHY Control Register 
#define VTPIO_CTL          *(unsigned int*)(0x01E2C000)                  // VTP IO Control Register

#define PD0                0   /*Power Domain-0*/
#define PD1                1   /*Power Domain-1*/
#define LPSC_DDR           6   /*PSC1*/

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  DDRConfig(unsigned int freq)                                            *
 *      Setup PLL1 for DDR Clock                                            *
 *                                                                          *
 * ------------------------------------------------------------------------ */
DDRConfig(unsigned int freq)
{
    int i;

    /* Enable DDRCTL SDRAM Clock */
    PSC1_LPSC_enable(PD0, LPSC_DDR);

    
    DDRCTL_PHYCTL =  0x00000000 
        |  0x1 << 6     // EXT_STRBEN - External strobe gating mode
        |  0x1 << 6     // PWRDNEN    - Power down receivers
        |  0x7 << 0;    // Read latency


    DDRCTL_SDCR    = 0x08D7C832;      // DDR Bank: 32-bit bus, CAS=5,
                                      // 8 banks, 1024-word pg, unlock

    DDRCTL_SDTIMR1 = 0
        |(16 << 25 )    // (127.5ns / 7.58ns) - 1 = TRFC  @ 132MHz
        |( 1 << 22 )    // (   15ns / 7.58ns) - 1 = TRP
        |( 1 << 19 )    // (   15ns / 7.58ns) - 1 = TRCD
        |( 1 << 16 )    // (   15ns / 7.58ns) - 1 = TWR
        |( 5 << 11 )    // (   40ns / 7.58ns) - 1 = TRAS
        |( 7 <<  6 )    // (   55ns / 7.58ns) - 1 = TRC
        |( 1 <<  3 )    // (  7.5ns / 7.58ns) - 1 = TRRD
        |( 1 <<  0 );   // (  7.5ns / 7.58ns) - 1 = TWTR

    DDRCTL_SDTIMR2 = 0
        |( 1 << 27 )    // (70000 / ( 1 / 7.8us)) - 1 = T_RASMAX
        |( 2 << 25 )    // txp < tcke => T_XP = tcke - 1 = 2
        |( 0 << 23 )    // T_ODT not supported
        |(18 << 16 )    // (137.5ns / 7.58ns) - 1 = T_XSNR
        |(199<<  8 )    // 200 - 1 = T_XSRD
        |( 1 <<  5 )    // (  7.5ns / 7.58ns) - 1 = T_RTP
        |( 2 <<  0 );   // tcke - 1 = 2
  
    DDRCTL_SDCR    &= ~0x00008000; // Clear TIMUNLOCK

    DDRCTL_SDCR2   = 0x00000000; // IBANK_POS set to 0 so this register does not apply
    DDRCTL_SDRCR   = 0
        |(1  << 31 )    // LPMODEN   - Enable low-power mode
        |(1  << 30 )    // MCLKSTOPEN - Enables MCLK stopping
        |(0  << 23 )    // SR_PD      - self-refresh mode
        |(1030<< 0 );   // RR         - SDRAM frequency/SDRAM refresh rate = 132M / (1 / 7.8u)

    // SyncReset the Clock to DDRCTL SDRAM 
    PSC1_LPSC_SyncReset(PD0, LPSC_DDR);

    // Enable the Clock to DDRCTL SDRAM
    PSC1_LPSC_enable(PD0, LPSC_DDR);

    DDRCTL_SDRCR &= ~0xC0000000;  // Disable self-refresh

}

menuitem "Test_setup"

hotmenu
Ethernet_MII_setup()
{
    GEL_TextOut( "Setup PINMUX Registers for Ethernet_MII" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

    PINMUX2  = 0x88888880;  // MII
    PINMUX3  = 0x88888888;  // MII
	PINMUX6  = 0x00000080;  // MII MDIO enable (BUFF_ENn)
    CFGCHIP3 &= ~0x00000100; // MII

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
}

hotmenu
Ethernet_RMII_setup()
{
    GEL_TextOut( "Setup PINMUX Registers for Ethernet_RMII" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

    PINMUX14 = 0x88888800;  // RMII  
    PINMUX15 = 0x00000080;  // RMII
    CFGCHIP3 |= 0x00000100; // RMII

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
}

hotmenu
LCD_setup()
{
    GEL_TextOut( "Setup PINMUX Registers for LCD" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

    PINMUX16  = 0x22222200;  // LCDIO
    PINMUX17  = 0x22222222;  // LCDIO
    PINMUX18  = 0x00000022;  // LCDIO
    PINMUX18 |= 0x22000000;  // LCD_MCLK, LCD_PCLK 
    PINMUX19  = 0x02000022;  // LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC
    PINMUX5   = 0x00000008;  // GP2[15]
    PINMUX5  |= 0x80000000;  // GP2[8]
    PINMUX6   = 0x00080080;  // BUFF_ENn, Touch INT

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
}

hotmenu
CHAR_Display_setup()
{
    GEL_TextOut( "Setup PINMUX Registers for Character Display" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

    PINMUX16  = 0x22222200;  // LCDIO
    PINMUX17  = 0x22222222;  // LCDIO
    PINMUX18  = 0x00000022;  // LCDIO
    PINMUX18 |= 0x22000000;  // LCD_MCLK, LCD_PCLK 
    PINMUX19  = 0x02000022;  // LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC
    PINMUX5   = 0x00000008;  // GP2[15]
    PINMUX5  |= 0x80000000;  // GP2[8]
    PINMUX6   = 0x00000080;  // BUFF_ENn

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
}

hotmenu
UART_setup()
{
    GEL_TextOut( "Setup PINMUX Registers for UART" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

    PINMUX0 = 0x44000000;
    PINMUX4 = 0x00220000;

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
}

hotmenu
SD_setup()
{
    GEL_TextOut( "Setup PINMUX Registers for SD card" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

    PINMUX10 = 0x88222222;
    PINMUX11 = 0x00000022;

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
}

hotmenu
SPI_setup()
{
    GEL_TextOut( "Setup PINMUX Registers for SPI" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

    PINMUX5   = 0x00111110;  // SPI pins
    PINMUX6   = 0x00000080;  // BUFF_ENn

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
}

#define PWRDN            *(unsigned int*) 0x01E2C018
hotmenu
SATA_setup()
{

    GEL_TextOut( "Setup PINMUX Registers for SATA" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

    PWRDN = 0x00;  // Enables SATA clock receiver

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
}

hotmenu
MCASP_AUDIO_setup()
{
    GEL_TextOut( "Setup PINMUX Registers for MCASP" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

    PINMUX0 = 0x00111111;
    PINMUX1 = 0x00011000;

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
}
hotmenu
NAND_setup()
{
    GEL_TextOut( "Setup PINMUX Registers for NAND" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

	PINMUX7  = 0x00110110;
	PINMUX9  = 0x11111111;
	PINMUX12 = 0x01100000;

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
}
hotmenu
NOR_setup()
{
    GEL_TextOut( "Setup PINMUX Registers for NOR" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

    PINMUX5  = 0x11000000;
    PINMUX6  = 0x01000001;
    PINMUX7  = 0x00110001;
    PINMUX8  = 0x11111111;
    PINMUX9  = 0x11111111;
    PINMUX10 = 0x11111111;
    PINMUX11 = 0x11111111;
    PINMUX12 = 0x11111111;

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
}
hotmenu
Video_setup()
{
    GEL_TextOut( "Setup PINMUX Registers for Video" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

    PINMUX14 = 0x11111111;
	PINMUX15 = 0x11111111;
	PINMUX16 = 0x11111111;
    PINMUX17 = 0x11111111;
	PINMUX18 = 0x00000011;
	PINMUX19 = 0x00111100;

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
}

hotmenu
ADC_DAC_setup()
{
    GEL_TextOut( "Setup PINMUX Registers for Video" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

	PINMUX13 = 0x48440000;
	PINMUX14 = 0x44444400;
	PINMUX15 = 0x44444444;
	PINMUX16 = 0x44444444;
	PINMUX17 = 0x44444444;
	PINMUX18 = 0x00444444;
    PINMUX19 = 0x00010000;

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
} 

hotmenu
USB_POWER_setup()
{
    GEL_TextOut( "Setup PINMUX Registers for USB Power Test" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

	PINMUX0 = 0x00000000;
	PINMUX6 = 0x00008000;
	CFGCHIP2 = 0x00002872;

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
} 

hotmenu
USB_TEST_setup()
{
    int i;
    GEL_TextOut( "Setup PINMUX Registers for USB Test\n" );
    KICK0R = 0x83e70b13;  // Kick0 register + data (unlock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (unlock) 

	PINMUX0 = 0x00000000;
	PINMUX6 = 0x00008000;

	/* Setup USB PHY */
    CFGCHIP2 |= 0x00008000; // Hold PHY in Reset
    for (i=0; i<50; i++);    // Drive Reset for few clock cycles
    CFGCHIP2 = 0x00004972;  // Internal USB clock, 24MHz system clock, out of reset 
    while( (CFGCHIP2 & 0x00020000) == 0); // Wait Until PHY Clock is Good
	GEL_TextOut( "USB PHY Initialized\n" );

    KICK0R = 0x83e70b13;  // Kick0 register + data (lock)
    KICK1R = 0x95a4f1e0;  // Kick1 register + data (lock) 
	GEL_TextOut( "[Done]\n" );
}