/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  evmdm368.gel                                                            *
 *  Version 0.01                                                            *
 *                                                                          *
 *  This GEL file is designed to be used in conjunction with                *
 *  CCStudio 3.3+ and the DM368 based EVM.                                  *
 *                                                                          *
 *  Version History                                                         *
 *  v0.01 - Initial Release                                                 *
 * ------------------------------------------------------------------------ */

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  StartUp( )                                                              *
 *      Setup Memory Map                                                    *
 *                                                                          *
 * ------------------------------------------------------------------------ */
StartUp( )
{
    Setup_Memory_Map( );
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Device System Controller                                                *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define SYSTEM_BASE         0x01C40000
#define PINMUX0             *(  unsigned int* )( SYSTEM_BASE + 0x00 )
#define PINMUX1             *(  unsigned int* )( SYSTEM_BASE + 0x04 )
#define PINMUX2             *(  unsigned int* )( SYSTEM_BASE + 0x08 )
#define PINMUX3             *(  unsigned int* )( SYSTEM_BASE + 0x0C )
#define PINMUX4             *(  unsigned int* )( SYSTEM_BASE + 0x10 )
#define BOOTCFG             *(  unsigned int* )( SYSTEM_BASE + 0x14 )
#define ARM_INTMUX          *(  unsigned int* )( SYSTEM_BASE + 0x18 )
#define EDMA_INTMUX         *(  unsigned int* )( SYSTEM_BASE + 0x1C )
#define DDR_SLEW            *(  unsigned int* )( SYSTEM_BASE + 0x20 )
#define UHPI_CTL            *(  unsigned int* )( SYSTEM_BASE + 0x24 )
#define DEVICE_ID           *(  unsigned int* )( SYSTEM_BASE + 0x28 )
#define VDAC_CONFIG         *(  unsigned int* )( SYSTEM_BASE + 0x2C )
#define TIMER64_CTL         *(  unsigned int* )( SYSTEM_BASE + 0x30 )
#define USBPHY_CTL          *(  unsigned int* )( SYSTEM_BASE + 0x34 )
#define MISC                *(  unsigned int* )( SYSTEM_BASE + 0x38 )
#define MSTPRI0             *(  unsigned int* )( SYSTEM_BASE + 0x3C )
#define MSTPRI1             *(  unsigned int* )( SYSTEM_BASE + 0x40 )
#define VPSS_CLKCTL         *(  unsigned int* )( SYSTEM_BASE + 0x44 )
#define PERI_CLKCTL         *(  unsigned int* )( SYSTEM_BASE + 0x48 )
#define DEEPSLEEP           *(  unsigned int* )( SYSTEM_BASE + 0x4C )
#define DFT_ENABLE          *(  unsigned int* )( SYSTEM_BASE + 0x50 )
#define DEBOUNCE0           *(  unsigned int* )( SYSTEM_BASE + 0x54 )
#define DEBOUNCE1           *(  unsigned int* )( SYSTEM_BASE + 0x58 )
#define DEBOUNCE2           *(  unsigned int* )( SYSTEM_BASE + 0x5C )
#define DEBOUNCE3           *(  unsigned int* )( SYSTEM_BASE + 0x60 )
#define DEBOUNCE4           *(  unsigned int* )( SYSTEM_BASE + 0x64 )
#define DEBOUNCE5           *(  unsigned int* )( SYSTEM_BASE + 0x68 )
#define DEBOUNCE6           *(  unsigned int* )( SYSTEM_BASE + 0x6C )
#define DEBOUNCE7           *(  unsigned int* )( SYSTEM_BASE + 0x70 )
#define VTPIO_CTL           *(  unsigned int* )( SYSTEM_BASE + 0x74 )
#define PUPDCTL0            *(  unsigned int* )( SYSTEM_BASE + 0x78 )
#define PUPDCTL1            *(  unsigned int* )( SYSTEM_BASE + 0x7C )
#define HDIMCOBT            *(  unsigned int* )( SYSTEM_BASE + 0x80 )
#define PLL0_CONFIG         *(  unsigned int* )( SYSTEM_BASE + 0x84 )
#define PLL1_CONFIG         *(  unsigned int* )( SYSTEM_BASE + 0x88 )

#define GPINT_GPEN			(unsigned int *) 0x01C21C08
#define GPTDAT_GPDIR		(unsigned int *) 0x01C21C0C

OnResetDetected()
{
    GEL_TextOut( "\nReset Detected - Reinitializing\n\n");
    OnTargetConnect();
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  OnTargetConnect( )                                                      *
 *      Setup PinMux, Power, PLLs, DDR, & EMIF                              *
 *                                                                          *
 * ------------------------------------------------------------------------ */
OnTargetConnect( )
{
    GEL_TextOut( "\nDM368 EVM ARM Startup Sequence\n\n" );

    Setup_Memory_Map();

    if ((*((unsigned int *)0x01C408E4)&3) != 0)	// Only initialize on cold boot (RSTYPE field)
    {
        // This block of code implements the VPSS Sync Reset Fix
        GEL_TextOut("VPSS Sync Reset Fix\n");
        VPSS_CLKCTL = 0x80;

        psc_change_state( 47 , 0 );
        psc_change_state( 47 , 1 );
        *GPINT_GPEN = 0x00020000;         
        *GPTDAT_GPDIR = 0x00020002;
    }
    /* Peripheral Clock control */
    PERI_CLKCTL = 0x0C3F0FF8;          // DDR2 clock source   : PLLC1SYSCLK7
                                       // ARM926 clock source : PLLC2SYSCLK2
    Disable_IRQ_Flush_Cache();         // Clean up system state
    Setup_Psc_All_On();
    Setup_Pin_Mux();                   // Setup Pin Mux
    Setup_PLL1();                      // Configure DDR
    Setup_PLL2();                      // Confogire ARM
    Setup_DDR2();                      // Configure DDR2 controller
    Setup_AEMIF();                     // Setup AEMIF (CE0 and CE1)

    GEL_TextOut( "\nStartup Complete.\n\n" );
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  OnPreFileLoaded( )                                                      *
 *      This function is called automatically when the 'Load Program'       *
 *      Menu item is selected.                                              *
 *                                                                          *
 * ------------------------------------------------------------------------ */
OnPreFileLoaded( )
{
    /*
     *  GEL_Reset() is used to deal with the worst case senario of
     *  unknown target state.  If for some reason a reset is not desired
     *  upon target connection, GEL_Reset() may be removed and replaced
     *  with something "less brutal" like a cache initialization
     *  function.
     */
    GEL_Reset();

    Disable_VPSS( );                    // Disable VPSS
    Disable_IRQ_Flush_Cache( );         // Clean up system state
    Disable_EDMA( );                    // Disable EDMA

    GEL_TextOut( "\n" );
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  OnRestart( )                                                            *
 *      This function is called by CCS when you do Debug->Restart.          *
 *      The goal is to put the C6x into a known good state with respect to  *
 *      cache, edma and interrupts.                                         *
 *      Failure to do this can cause problems when you restart and          *
 *      run your application code multiple times.  This is different        *
 *      then OnPreFileLoaded() which will do a GEL_Reset() to get the       *
 *      C6x into a known good state.                                        *
 *                                                                          *
 * ------------------------------------------------------------------------ */
OnRestart( int nErrorCode )
{
//    Disable_IRQ_Flush_Cache( );         // Clean up system state
//    Disable_EDMA( );                    // Disable EDMA

    GEL_TextOut( "\n" );
}

menuitem "DM365 EVM Memory Map";

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_Memory_Map( )                                                     *
 *      Setup the Memory Map for ARM side only.                             *
 *                                                                          *
 * ------------------------------------------------------------------------ */
hotmenu
Setup_Memory_Map( )
{
    GEL_MapOn( );
    GEL_MapReset( );

    /* ARM RAM & ROM */
    GEL_MapAddStr( 0x00000000, 0, 0x00004000, "R|W|AS4", 0 );   // ARM RAM0 Instruction
    GEL_MapAddStr( 0x00004000, 0, 0x00004000, "R|W|AS4", 0 );   // ARM RAM1 Instruction
    GEL_MapAddStr( 0x00008000, 0, 0x00008000, "R|AS4",   0 );   // ARM ROM Instruction
    GEL_MapAddStr( 0x00010000, 0, 0x00004000, "R|W|AS4", 0 );   // ARM RAM0 Data
    GEL_MapAddStr( 0x00014000, 0, 0x00004000, "R|W|AS4", 0 );   // ARM RAM1 Data
    GEL_MapAddStr( 0x00018000, 0, 0x00008000, "R|AS4",   0 );   // ARM ROM Data

    /* Extend Trace */
    GEL_MapAddStr( 0x01bc0000, 0, 0x00001900, "R|W|AS4", 0 );   // ARM ETB

    /* Peripherals */
    GEL_MapAddStr( 0x01c00000, 0, 0x00000644, "R|W|AS4", 0 );   // EDMA Channel Ctrl
    GEL_MapAddStr( 0x01c01000, 0, 0x00000098, "R|W|AS4", 0 );   // EDMA Channel Ctrl
    GEL_MapAddStr( 0x01c02000, 0, 0x00000098, "R|W|AS4", 0 );   // EDMA Channel Ctrl
    GEL_MapAddStr( 0x01c02200, 0, 0x00000098, "R|W|AS4", 0 );   // EDMA Channel Ctrl
    GEL_MapAddStr( 0x01c10000, 0, 0x000003d8, "R|W|AS4", 0 );   // EDMA Transfer Ctrl 0
    GEL_MapAddStr( 0x01c10400, 0, 0x000003d8, "R|W|AS4", 0 );   // EDMA Transfer Ctrl 1
    GEL_MapAddStr( 0x01c10800, 0, 0x00000400, "R|W|AS4", 0 );   // EDMA Transfer Ctrl 2
    GEL_MapAddStr( 0x01c10C00, 0, 0x00000400, "R|W|AS4", 0 );   // EDMA Transfer Ctrl 3
    GEL_MapAddStr( 0x01c20000, 0, 0x00000034, "R|W|AS4", 0 );   // UART 0
   
    GEL_MapAddStr( 0x01c20800, 0, 0x00000400, "R|W|AS4", 0 );   // Timer 4/5
    GEL_MapAddStr( 0x01c20C00, 0, 0x00000400, "R|W|AS4", 0 );   // RTO
    GEL_MapAddStr( 0x01c21000, 0, 0x0000003c, "R|W|AS4", 0 );   // I2C
    GEL_MapAddStr( 0x01c21400, 0, 0x00000028, "R|W|AS4", 0 );   // Timer 0/1
    GEL_MapAddStr( 0x01c21800, 0, 0x00000028, "R|W|AS4", 0 );   // Timer 2/3
    GEL_MapAddStr( 0x01c21c00, 0, 0x0000002c, "R|W|AS4", 0 );   // WDT
    GEL_MapAddStr( 0x01c22000, 0, 0x0000001c, "R|W|AS4", 0 );   // PWM 0
    GEL_MapAddStr( 0x01c22400, 0, 0x0000001c, "R|W|AS4", 0 );   // PWM 1
    GEL_MapAddStr( 0x01c22800, 0, 0x0000001c, "R|W|AS4", 0 );   // PWM 2
    GEL_MapAddStr( 0x01c22C00, 0, 0x0000001c, "R|W|AS4", 0 );   // PWM 3
    GEL_MapAddStr( 0x01c23000, 0, 0x00000800, "R|W|AS4", 0 );   // SPI4
    GEL_MapAddStr( 0x01C23800, 0, 0x00000400, "R|W|AS4", 0 );   // Timer 6/7
    GEL_MapAddStr( 0x01C23C00, 0, 0x00000400, "R|W|AS4", 0 );   // A/D Converter Interface    
    GEL_MapAddStr( 0x01c40000, 0, 0x00000800, "R|W|AS4", 0 );   // System Module
    GEL_MapAddStr( 0x01c40800, 0, 0x00000400, "R|W|AS4", 0 );   // PLL 1
    GEL_MapAddStr( 0x01c40c00, 0, 0x00000400, "R|W|AS4", 0 );   // PLL 2
    GEL_MapAddStr( 0x01c41000, 0, 0x00001000, "R|W|AS4", 0 );   // PSC Domain Control
    GEL_MapAddStr( 0x01C42000, 0, 0x00000400, "R|W|AS4", 0 );   // System DFT    
    GEL_MapAddStr( 0x01c48000, 0, 0x00000050, "R|W|AS4", 0 );   // ARM Interrupts
    GEL_MapAddStr( 0x01c64000, 0, 0x00002000, "R|W|AS4", 0 );   // USB 2.0 + RAM
    GEL_MapAddStr( 0x01c66000, 0, 0x00000074, "R|W|AS4", 0 );   // SPI0
    GEL_MapAddStr( 0x01c66800, 0, 0x00000074, "R|W|AS4", 0 );   // SPI1
    GEL_MapAddStr( 0x01c67000, 0, 0x00000038, "R|W|AS4", 0 );   // GPIO
    GEL_MapAddStr( 0x01c67800, 0, 0x00000074, "R|W|AS4", 0 );   // SPI2
    GEL_MapAddStr( 0x01C68000, 0, 0x00000800, "R|W|AS4", 0 );   // SPI3
    GEL_MapAddStr( 0x01C69000, 0, 0x00000400, "R|W|AS4", 0 );   // RTC (Real time clk)
    GEL_MapAddStr( 0x01C69400, 0, 0x00000400, "R|W|AS4", 0 );   // Keyscan
    GEL_MapAddStr( 0x01C69800, 0, 0x00000800, "R|W|AS4", 0 );   // UHPI (Universal Host Port Interface)
    GEL_MapAddStr( 0x01c70000, 0, 0x00010000, "R|W|AS4", 0 );   // VPSS
    GEL_MapAddStr( 0x01ca0000, 0, 0x00020000, "R|W|AS4", 0 );   // IMCOP
    GEL_MapAddStr( 0x01D00000, 0, 0x00000078, "R|W|AS4", 0 );   // MMC / SD1
    GEL_MapAddStr( 0x01d02000, 0, 0x00002000, "R|W|AS4", 0 );   // McBSP
    GEL_MapAddStr( 0x01D06000, 0, 0x00000034, "R|W|AS4", 0 );   // UART 1
    GEL_MapAddStr( 0x01D07000, 0, 0x00001000, "R|W|AS4", 0 );   // EMAC Control Regs
    GEL_MapAddStr( 0x01D08000, 0, 0x00002000, "R|W|AS4", 0 );   // EMAC Wrap RAM 
    GEL_MapAddStr( 0x01D0A000, 0, 0x00001000, "R|W|AS4", 0 );   // EMAC Wrap Ctll Regs 
    GEL_MapAddStr( 0x01D0B000, 0, 0x00000800, "R|W|AS4", 0 );   // EMAC MDIO
    GEL_MapAddStr( 0x01D0C000, 0, 0x00000400, "R|W|AS4", 0 );   // VoiceCodec 
    GEL_MapAddStr( 0x01d10000, 0, 0x000000b4, "R|W|AS4", 0 );   // EMIFA Control
    GEL_MapAddStr( 0x01d11000, 0, 0x00000078, "R|W|AS4", 0 );   // MMC / SD0
    GEL_MapAddStr( 0x01E00000, 0, 0x00019000, "R|W|AS4", 0 );   // Kaleido Coprocessor

    /* Off-chip */
    GEL_MapAddStr( 0x02000000, 0, 0x02000000, "R|W|AS1", 0 );   // AEMIF CE0
    GEL_MapAddStr( 0x04000000, 0, 0x02000000, "R|W|AS1", 0 );   // AEMIF CE1

    /* DDR2 */
    GEL_MapAddStr( 0x20000000, 0, 0x000000f4, "R|W|AS4", 0 );   // DDR2 Control
    GEL_MapAddStr( 0x80000000, 0, 0x10000000, "R|W|AS4", 0 );   // DDR2 SDRAM
}


/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Clear_Memory_Map( )                                                     *
 *      Clear the Memory Map                                                *
 *                                                                          *
 * ------------------------------------------------------------------------ */
hotmenu
Clear_Memory_Map( )
{
    GEL_MapOff( );
    GEL_MapReset( );
}

menuitem "DM365 EVM Functions";


/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Flush_Cache_Disable_MMU( )                                              *
 *      Flush Cache & Disable MMU                                           *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Disable_IRQ_Flush_Cache( )
{
    #define INTC_FIQ0            *( int* )( 0x01c48000 )
    #define INTC_FIQ1            *( int* )( 0x01c48004 )
    #define INTC_IRQ0            *( int* )( 0x01c48008 )
    #define INTC_IRQ1            *( int* )( 0x01c4800c )
    #define INTC_EINT0           *( int* )( 0x01c48018 )
    #define INTC_EINT1           *( int* )( 0x01c4801c )
    #define INTC_INTCTL          *( int* )( 0x01c48020 )
    #define INTC_EABASE          *( int* )( 0x01c48024 )

    GEL_TextOut( "Disable IRQ/FIQ\n" );
    CPSR = 0x400000D3;                  // Set to supervisor mode, disable IRQ/FIQ

    GEL_TextOut( "Flush Cache\n" );
    REG_CP15_FLSH_DI;                   // Flush then disable D-Cache & I-Cache
    REG_CP15_I_CACHE = 1;
    REG_CP15_D_CACHE = 1;

    GEL_TextOut( "Disable MMU\n" );
    REG_CP15_MMU = 0;                   // Disable MMU

    INTC_INTCTL = 4;                    // Disable ARM interrupts
    INTC_EABASE = 0;
    INTC_EINT0 = 0;
    INTC_EINT1 = 0;

    INTC_FIQ0 = 0xffffffff;
    INTC_FIQ1 = 0xffffffff;
    INTC_IRQ0 = 0xffffffff;
    INTC_IRQ1 = 0xffffffff;

    _wait( 200 );
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Disable_VPSS( )                                                         *
 *      Disable VPFE & VPBE                                                 *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Disable_VPSS( )
{
    #define ISIF_SYNCEN         *( unsigned int* )( 0x01C71000 )
    #define VPBE_PCR            *( unsigned int* )( 0x01C72704 )
    #define VPBE_VENC_VMOD      *( unsigned int* )( 0x01C72400 )
    #define VPBE_OSD_MODE       *( unsigned int* )( 0x01C72600 )

    GEL_TextOut( "Disable VPSS\n" );

	ISIF_SYNCEN = 0;              // Disable VPFE
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Disable_EDMA( )                                                         *
 *      Disabe EDMA events and interrupts, clear any pending events         *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Disable_EDMA( )
{
    #define EDMA_3CC_IECRH          *( int* )( 0x01C0105C )
    #define EDMA_3CC_EECRH          *( int* )( 0x01C0102C )
    #define EDMA_3CC_ICRH           *( int* )( 0x01C01074 )
    #define EDMA_3CC_ECRH           *( int* )( 0x01C0100C )

    #define EDMA_3CC_IECR           *( int* )( 0x01C01058 )
    #define EDMA_3CC_EECR           *( int* )( 0x01C01028 )
    #define EDMA_3CC_ICR            *( int* )( 0x01C01070 )
    #define EDMA_3CC_ECR            *( int* )( 0x01C01008 )

    GEL_TextOut( "Disable EDMA events\n" );
    EDMA_3CC_IECRH  = 0xFFFFFFFF;   // IERH ( disable high interrupts )
    EDMA_3CC_EECRH  = 0xFFFFFFFF;   // EERH ( disable high events )
    EDMA_3CC_ICRH   = 0xFFFFFFFF;   // ICRH ( clear high interrupts )
    EDMA_3CC_ECRH   = 0xFFFFFFFF;   // ICRH ( clear high events )

    EDMA_3CC_IECR   = 0xFFFFFFFF;   // IER  ( disable low interrupts )
    EDMA_3CC_EECR   = 0xFFFFFFFF;   // EER  ( disable low events )
    EDMA_3CC_ICR    = 0xFFFFFFFF;   // ICR  ( clear low interrupts )
    EDMA_3CC_ECR    = 0xFFFFFFFF;   // ICRH ( clear low events )
}


/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_Pin_Mux( )                                                        *
 *      Configure Pin Multiplexing                                          *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Setup_Pin_Mux( )
{
    GEL_TextOut( "Setup PinMux... " );

    PINMUX0 = 0x00FD0000;  // Video Yin, SD0, McBSP, SD1_CLK
    PINMUX1 = 0x00145555;  // Video Cout, EXTCLK, FIELD
    PINMUX2 = 0x00000055;  // EMIFA
    PINMUX3 = 0x375AFFFF;  // SPI0, I2C, UART0, ENET, MDIO
    PINMUX4 = 0x55556555;  // SD1, SPI1, SPI2, SPI4, USBDRVVBUS    

    GEL_TextOut( "[Done]\n" );
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_Psc_All_On( )                                                     *
 *      Enable all PSC modules.                                             *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Setup_Psc_All_On( )
{
    int i;
    GEL_TextOut( "Setup Power Modules (All on)... " );

    /*
     *  Enable all non-reserved power modules
     */
    for ( i = 0 ; i <= 40 ; i++ )
        psc_change_state( i , 3 );
    for ( i = 42 ; i <= 47 ; i++ )
        psc_change_state( i , 3 );
    for ( i = 48 ; i <= 51 ; i++ )
        psc_change_state( i , 3 );
    psc_change_state( 41 , 3 );

    GEL_TextOut( "[Done]\n" );
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  psc_change_state( id, state )                                           *
 *      id    = Domain #ID                                                  *
 *      state = ( ENABLE, DISABLE, SYNCRESET, RESET )                       *
 *              (   =3  ,   =2   ,    =1    ,   =0  )                       *
 *                                                                          *
 * ------------------------------------------------------------------------ */
psc_change_state( int id, int state )
{
    #define PSC_PTCMD           *( unsigned int* )( 0x01c41120 )
    #define PSC_PTSTAT          *( unsigned int* )( 0x01c41128 )
    int* mdstat                 = ( int* )( 0x01c41800 + ( 4 * id ) );
    int* mdctl                  = ( int* )( 0x01c41a00 + ( 4 * id ) );
    int set_interrupt;

    /*
     *  Step 0 - Ignore request if the state is already set as is
     */
    if ( ( ( *mdstat ) & 0x1f ) == state )
        return;

    /*
     *  Step 1 - Wait for PTSTAT.GOSTAT to clear
     */
    while( PSC_PTSTAT & 1 );

    /*
     *  Step 2 - Set MDCTLx.NEXT to new state
     */
    *mdctl &= ~0x1f;
    *mdctl |= state;

    /*
     *  Step 3 - Start power transition ( set PTCMD.GO to 1 )
     */
    PSC_PTCMD |= 1;

    /*
     *  Step 4 - Wait for PTSTAT.GOSTAT to clear
     */
    while( PSC_PTSTAT & 1 );
}

_wait( int delay )
{
    int i;
    for( i = 0 ; i < delay ; i++ ){}
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_PLL1( )                                                           *
 *  CLKIN   = 24MHz                                                         *
 *  PLLOUT = (OSCIN / prediv) * ((pllm * 2) / postdiv) 
 *         = (24/4) * (72 * 2 / 1) 
 *         = 864MHz                                                         * 
 *                                                                          *
 * ------------------------------------------------------------------------ */
Setup_PLL1()
{
    unsigned int* pll_ctl       = ( unsigned int* )( 0x01c40900 );
    unsigned int* pll_secctl    = ( unsigned int* )( 0x01c40908 );
    unsigned int* pll_pllm      = ( unsigned int* )( 0x01c40910 );
    unsigned int* pll_prediv    = ( unsigned int* )( 0x01c40914 );
    unsigned int* pll_cmd       = ( unsigned int* )( 0x01c40938 );
    unsigned int* pll_stat      = ( unsigned int* )( 0x01c4093c );
    unsigned int* pll_div1      = ( unsigned int* )( 0x01c40918 );
    unsigned int* pll_div2      = ( unsigned int* )( 0x01c4091c );
    unsigned int* pll_div3      = ( unsigned int* )( 0x01c40920 );
    unsigned int* pll_postdiv   = ( unsigned int* )( 0x01c40928 );
    unsigned int* pll_div4      = ( unsigned int* )( 0x01c40960 );
    unsigned int* pll_div5      = ( unsigned int* )( 0x01c40964 );
    unsigned int* pll_div6      = ( unsigned int* )( 0x01c40968 );
    unsigned int* pll_div7      = ( unsigned int* )( 0x01c4096C );
    unsigned int* pll_div8      = ( unsigned int* )( 0x01c40970 );
    unsigned int* pll_div9      = ( unsigned int* )( 0x01c40974 );

    GEL_TextOut( "Setup PLL1... " );

    *pll_ctl &= ~0x0002;              // Power up PLL
    *pll_ctl |=  0x0010;              // Put PLL in disable mode
    *pll_ctl &= ~0x0010;              // Take PLL out of disable mode

    *pll_ctl &= ~0x0100;             // Onchip Oscillator
//    *pll_ctl |= 0x0100;              // External Oscillator
    *pll_ctl &= ~0x0020;             // Clear PLLENSRC
    *pll_ctl &= ~0x0001;             // Set PLL in bypass
    _wait( 150 );

    *pll_ctl |= 0x0008;              // Assert PLL reset
    *pll_ctl &= ~0x0008;             // Take PLL out of reset

    *pll_ctl &= ~0x0010;             // Enable PLL
    _wait( 150 );                    // Wait for PLL to stabilize

    *pll_pllm   =   72;          // Multiplier value = 2xPLLM
    *pll_prediv =   0x8003;      // Ratio value = RATIO + 1

    _wait (100 );

    *pll_secctl  = 0x00470000;   // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 
    *pll_secctl  = 0x00460000;   // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 
    *pll_secctl  = 0x00400000;   // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 
    *pll_secctl  = 0x00410000;   // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1
    *pll_postdiv = 0x8000;  


    *pll_div1    = 0x8018;   // 864/24 = 36MHz  -> USB (Use AUXCLK from USB PHY Control register)
	*pll_div2    = 0x8001;   // 864/2  = 432mhz -> ARM926/HDVICP(Internal)
    *pll_div3    = 0x8002;   // 864/3  = 288Mhz -> MJCP/HDVICP(Bus)
    *pll_div4    = 0x8005;   // 864/6  = 144Mhz -> EDMA/Peripheral CFG0
    *pll_div5    = 0x8002;   // 864/3  = 288Mhz -> VPSS
    *pll_div6    = 0x801F;   // 864/32 = 27Mhz  -> VENC alternate for SD
    *pll_div8    = 0x8008;   // 864/9  = 96MHz  -> MMC0/SD0
    *pll_div9    = 0x8001;   // 864/4  = 216MHz -> CLKOUT2

    *pll_cmd |= 0x0001;      // Set GOSET

    _wait( 2000 );

    while(! (((PLL0_CONFIG) & 0x07000000) == 0x07000000));  // Wait for PLL to lock

    _wait( 2000 );
    *pll_ctl = 0x0001;       // Enable PLL

    GEL_TextOut( "[Done]\n" );
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_PLL2( )                                                           *
 *                                                                          *
 *  CLKIN =   24MHz                                                         *
 *  PLLOUT = (OSCIN / prediv) * ((pllm * 2) / postdiv) 
 *         = (24/6) * (85 * 2 / 1) 
 *         = 680MHz                                                         *  
 *                                                                          *
 * ------------------------------------------------------------------------ */
Setup_PLL2()
{
    unsigned int* pll_ctl       = ( unsigned int* )( 0x01c40d00 );
    unsigned int* pll_secctl    = ( unsigned int* )( 0x01c40d08 );
    unsigned int* pll_pllm      = ( unsigned int* )( 0x01c40d10 );
    unsigned int* pll_prediv    = ( unsigned int* )( 0x01c40d14 );
    unsigned int* pll_cmd       = ( unsigned int* )( 0x01c40d38 );
    unsigned int* pll_stat      = ( unsigned int* )( 0x01c40d3c );
    unsigned int* pll_div1      = ( unsigned int* )( 0x01c40d18 );
    unsigned int* pll_div2      = ( unsigned int* )( 0x01c40d1c );
    unsigned int* pll_div3      = ( unsigned int* )( 0x01c40d20 );
    unsigned int* pll_postdiv   = ( unsigned int* )( 0x01c40d28 );
    unsigned int* pll_div4      = ( unsigned int* )( 0x01c40d60 );
    unsigned int* pll_div5      = ( unsigned int* )( 0x01c40d64 );
    unsigned int* pll_bpdiv     = ( unsigned int* )( 0x01c40d2c );

    GEL_TextOut( "Setup PLL2... " );

    *pll_ctl &= ~0x0002;              // Power up PLL
    *pll_ctl |=  0x0010;              // Put PLL in disable mode
    *pll_ctl &= ~0x0010;              // Take PLL out of disable mode

    *pll_ctl &= ~0x0100;             // Onchip Oscillator
//    *pll_ctl |= 0x0100;              // External Oscillator
    *pll_ctl &= ~0x0020;             // Clear PLLENSRC
    *pll_ctl &= ~0x0001;             // Set PLL in bypass
    _wait( 150 );

    *pll_ctl |= 0x0008;              // Assert PLL reset
    *pll_ctl &= ~0x0008;             // Take PLL out of reset

    *pll_ctl &= ~0x0010;             // Enable PLL
    _wait( 150 );                    // Wait for PLL to stabilize

    *pll_pllm   =   85;          // Multiplier value = 2xPLLM
    *pll_prediv =   0x8005;      // Ratio value = RATIO + 1
 
    *pll_postdiv = 0x8000;
   
    *pll_secctl = 0x00470000;        // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 
    *pll_secctl = 0x00460000;        // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 
    *pll_secctl = 0x00400000;        // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 
    *pll_secctl = 0x00410000;        // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1
			     
    //Divider setting for PLL2 
    *pll_div3    = 0x8000;   // 680/2  = 340Mhz   -> DDR (DDR has internal /2 divider)
    *pll_div4    = 0x8005;   // 680/6  = 99MHz    -> VOICE (Use PERI_CLKCTL.DIV2 to get 16 kHz*256=4.096MHz input clock)
    *pll_div5    = 0x8008;   // 680/9  = 75.5Mhz  -> VENC for HD video  

    *pll_cmd |= 0x0001;              // Set GOSET
    while( ( *pll_stat & 1 ) != 0 ); // Wait until complete

    _wait( 2000 );

    while(! (((PLL1_CONFIG) & 0x07000000) == 0x07000000));  // Wait for PLL to lock
    
    _wait( 2000 );
    *pll_ctl |= 0x0001;              // Enable PLL

    GEL_TextOut( "[Done]\n" );
}


#define	DDR_BASE         0x20000000
#define EIDRR            (unsigned int*)(DDR_BASE + 0x00)    		//EMIF Module ID and Revision Register                                    
#define SDSTAT           (unsigned int*)(DDR_BASE + 0x04)    		//SDRAM Status Register  
#define SDCFG1           (unsigned int*)(DDR_BASE + 0x08) 	  		//SDRAM Bank Config Register
#define SDREF            (unsigned int*)(DDR_BASE + 0x0C) 	  		//SDRAM Refresh Control Register
#define SDTIM0           (unsigned int*)(DDR_BASE + 0x10) 	  		//SDRAM Timing Register
#define SDTIM1           (unsigned int*)(DDR_BASE + 0x14) 	  		//SDRAM Timing Register
#define SDCFG2           (unsigned int*)(DDR_BASE + 0x1C) 	  		//SDRAM Config Register 2
#define VBUSMP           (unsigned int*)(DDR_BASE + 0x20) 	  		//VBUSM Burst Priority Register
#define VBUSMCFG1        (unsigned int*)(DDR_BASE + 0x28) 	  		//VBUSM config Value1 Register
#define VBUSMCFG2        (unsigned int*)(DDR_BASE + 0x2c) 	  		//VBUSM config Value2 Register
#define PERFCNT1		 (unsigned int*)(DDR_BASE + 0x40)	  		//Performance Counter Register 1
#define PERFCNT2		 (unsigned int*)(DDR_BASE + 0x44)	  		//Performance Counter Register 2
#define PERFCNTCFG		 (unsigned int*)(DDR_BASE + 0x48)    		//Performance Counter Config Register
#define PERFCNTMSTREGSEL (unsigned int*)(DDR_BASE + 0x4C)	  		//Performance Counter Master Region Select Register
#define INTRAW			 (unsigned int*)(DDR_BASE + 0xC0)    		//Interrupt Raw Register
#define INTMASK          (unsigned int*)(DDR_BASE + 0xC4)    		//Interrupt Masked Register
#define INTMASKSET       (unsigned int*)(DDR_BASE + 0xC8)    		//Interrupt Mask Set Register
#define INTMASKCLR       (unsigned int*)(DDR_BASE + 0xCC)    		//Interrupt Mask Clear Register
#define DDRPHYREV        (unsigned int*)(DDR_BASE + 0xE0)    		//DDR PHY ID and Revision Register
#define DDRPHYCTL1       (unsigned int*)(DDR_BASE + 0xE4)    		//DDR PHY Control Register 1
#define DDRPHYCTL2       (unsigned int*)(DDR_BASE + 0xE8)    		//DDR PHY Control Register 2



/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_DDR2( )                                                           *
 *      Configure DDR2 to run at 200MHz.                                    *
 *                                                                          *
 * ------------------------------------------------------------------------ */

#define DDR_SDBCR           *( unsigned int* )( 0x20000008 )
#define DDR_SDRCR           *( unsigned int* )( 0x2000000c )
#define DDR_SDTIMR          *( unsigned int* )( 0x20000010 )
#define DDR_SDTIMR2         *( unsigned int* )( 0x20000014 )
#define DDR_DDRPHYCR        *( unsigned int* )( 0x200000e4 )

#define DDR_VTPIOCR         *( unsigned int* )( 0x200000f0 )
#define DDR_DDRVTPR         *( unsigned int* )( 0x01c42030 )
#define DDR_DDRVTPER        *( unsigned int* )( 0x01c4004c )
#define DDR_PHY_VTP_IOCTRL  *( unsigned int* )( 0x01C40074 ) // DDR PHY VTP adjust    (Read only)

Setup_DDR2( )
{
    int j;

    GEL_TextOut( "Setup DDR2... (340MHz)\n" );

	// VTP Caliberation
	//PWR_DWN bit is made '0', to power the VTP module 

    DDR_PHY_VTP_IOCTRL = DDR_PHY_VTP_IOCTRL & 0xFFFF9F3F;
  
    // Set bit CLRZ (bit 13)
    DDR_PHY_VTP_IOCTRL = DDR_PHY_VTP_IOCTRL | 0x00002000;
  
    // Check VTP READY Status
    while( !(DDR_PHY_VTP_IOCTRL & 0x8000));      
  
    // Set bit LOCK(bit7) and PWRSAVE (bit8)
    DDR_PHY_VTP_IOCTRL = DDR_PHY_VTP_IOCTRL | 0x00000080;     
    
    // Powerdown VTP as it is locked (bit 6)
    // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
    DDR_PHY_VTP_IOCTRL = DDR_PHY_VTP_IOCTRL | 0x00004040; 

    // DDR2 configuration for 243MHz clock
    *DDRPHYCTL1 = 0x000000C6;    // External DQS gatin enabled
                                 // ReadLatency: 0x5 (Taken as 5+1 =6 DDR_CLKP cycles)
   	*SDCFG1     = 0x0853C832;		
    *SDREF      = 0x00000768;    // Program SDRAM Refresh Control Register
    *VBUSMP     = 0x000000FE;	 // VBUSM Burst Priority Register, pr_old_count = 0xFE
    *SDTIM0     = 0       // Program SDRAM Timing Control Register1
    |( 43 << 25 )         // T_RFC = (trfc/DDR_CLK) - 1 = (127.5 / 2.941) - 1
    |( 5  << 22 )         // T_RP  = (trp/DDR_CLK) - 1  = (15 / 2.941) - 1
	|( 5  << 19 )         // T_RCD = (trcd/DDR_CLK) - 1 = (15 / 2.941) - 1
	|( 5  << 16 )         // T_WR  = (twr/DDR_CLK) - 1  = (15 / 2.941) - 1
	|( 13 << 11 )         // T_RAS = (tras/DDR_CLK) - 1 = (40 / 2.941) - 1
	|( 18 <<  6 )         // T_RC  = (trc/DDR_CLK) - 1  = (55 / 2.941) - 1
	|( 3  <<  3 )         // T_RRD = (trrd/DDR_CLK) - 1 = (10 / 2.941) - 1
    |( 2  <<  0 );        // T_WTR = (twtr/DDR_CLK) - 1 = (10 / 2.941) - 1

    *SDTIM1     = 0       // Program SDRAM Timing Control Register2
    |( 8  << 27 )         // T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
    |( 2  << 25 )         // T_XP  = tCKE - 1 = 3 - 2
    |( 46 << 16 )         // T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (137.5 / 2.941) - 1
    |( 199<<  8 )         // T_XSRD = txsrd - 1 = 200 - 1
    |(  2 <<  5 )         // T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
    |(  2 <<  0 );        // T_CKE = tcke - 1     = 3 - 1

    *SDCFG1     = 0x08534832;    // Program SDRAM Bank Config Register

    psc_change_state( 13 , 1 );
    psc_change_state( 13 , 3 );

    GEL_TextOut("DDR2 init is done for 16-bit Interface \n");  
    GEL_TextOut( "[Done]\n" );
}


/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  setup_aemif( )                                                          *
 *      Setup Async-EMIF to the specified timings using either NAND HW      *
 *      controller or normal EMIF controller                                *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define AEMIF_AWCCR             *( unsigned int* )( 0x01d10004 )
#define AEMIF_A1CR              *( unsigned int* )( 0x01d10010 )
#define AEMIF_A2CR              *( unsigned int* )( 0x01d10014 )
#define AEMIF_A3CR              *( unsigned int* )( 0x01d10018 )
#define AEMIF_A4CR              *( unsigned int* )( 0x01d1001C )
#define AEMIF_NANDFCR           *( unsigned int* )( 0x01d10060 )

Setup_AEMIF( )
{
    /* EMIF configuration for J7 in NAND mode */
    /* Use extended wait cycles to keep CE low during NAND access */
    AEMIF_AWCCR = 0xff;

    /* Setup CE0 - 8-bit NAND, 9.26ns/cycle */
    AEMIF_A1CR = 0x40400204;  // Setup=0, Strobe=4, Hold=0, TA=1, 8-bit
    AEMIF_NANDFCR |= 1;

    /* Setup CE1 - 8-bit normal async, 9.26ns/cycle */
    AEMIF_A2CR = 0x00a00504;  // Setup=0, Strobe=A, Hold=0, TA=1, 8-bit
    AEMIF_NANDFCR &= ~2;
}