/* --------------------------------------------------------------- * TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION * Created 2008, (C) Copyright 2008 Texas Instruments. All rights reserved * * ARM GEL File for 729MHz TMS320DM6467. * * ---------------------------------------------------------------*/ #define ARM_RAM0_I_MEM 0x00000004 #define ARM_RAM1_I_MEM 0x00004004 #define ARM_RAM0_D_MEM 0x00010004 #define ARM_RAM1_D_MEM 0x00014004 #define DSP_L2RAM_MEM 0x11818000 #define DSP_L1P_RAM_MEM 0x11E00000 #define DSP_L1D_RAM_MEM 0x11F00000 #define AEMIF_DATA_CS2_MEM 0x42000000 #define AEMIF_DATA_CS3_MEM 0x44000000 #define AEMIF_DATA_CS4_MEM 0x46000000 #define AEMIF_DATA_CS5_MEM 0x48000000 #define DDR_MEM 0x80000000 #define AEMIF_ADDR 0x20008000 #define RCSR (AEMIF_ADDR + 0x00) //Revision Code and Status Register #define WAITCFG (AEMIF_ADDR + 0x04) //Async Wait Cycle Config Register #define ACFG2 (AEMIF_ADDR + 0x10) //Async Bank1 Config Register #define ACFG3 (AEMIF_ADDR + 0x14) //Async Bank2 Config Register #define ACFG4 (AEMIF_ADDR + 0x18) //Async Bank3 Config Register #define ACFG5 (AEMIF_ADDR + 0x1C) //Async Bank4 Config Register #define AINTRAW (AEMIF_ADDR + 0x40) //Interrpt Raw Register #define AINTMASK (AEMIF_ADDR + 0x44) //Interrupt Masked Register #define AINTMASKSET (AEMIF_ADDR + 0x48) //Interrupt Mask Set Register #define INTMASKCLEAR (AEMIF_ADDR + 0x4C) //Interrupt Mask Clear Register #define NANDCTL (AEMIF_ADDR + 0x60) //NAND Flash Control Register #define NANDSTAT (AEMIF_ADDR + 0x64) //NAND Flash Status Register #define NANDECC2 (AEMIF_ADDR + 0x70) //NAND Flash 1 ECC Register #define NANDECC3 (AEMIF_ADDR + 0x74) //NAND Flash 2 ECC Register #define NANDECC4 (AEMIF_ADDR + 0x78) //NAND Flash 3 ECC Register #define NANDECC5 (AEMIF_ADDR + 0x7C) //NAND Flash 4 ECC Register #define DDR_BASE 0x20000000 #define EIDRR (DDR_BASE + 0x00) //EMIF Module ID and Revision Register #define SDSTAT (DDR_BASE + 0x04) //SDRAM Status Register #define SDCFG (DDR_BASE + 0x08) //SDRAM Bank Config Register #define SDREF (DDR_BASE + 0x0C) //SDRAM Refresh Control Register #define SDTIM0 (DDR_BASE + 0x10) //SDRAM Timing Register #define SDTIM1 (DDR_BASE + 0x14) //SDRAM Timing Register #define VBUSP (DDR_BASE + 0x20) //VBUSM Burst Priority Register #define PERFCNT1 (DDR_BASE + 0x40) //Performance Counter Register 1 #define PERFCNT2 (DDR_BASE + 0x44) //Performance Counter Register 2 #define PERFCNTCFG (DDR_BASE + 0x48) //Performance Counter Config Register #define PERFCNTMSTREGSEL (DDR_BASE + 0x4C) //Performance Counter Master Region Select Register #define INTRAW (DDR_BASE + 0xC0) //Interrupt Raw Register #define INTMASK (DDR_BASE + 0xC4) //Interrupt Masked Register #define INTMASKSET (DDR_BASE + 0xC8) //Interrupt Mask Set Register #define INTMASKCLR (DDR_BASE + 0xCC) //Interrupt Mask Clear Register #define DDRPHYREV (DDR_BASE + 0xE0) //DDR PHY ID and Revision Register #define DDRCTL1 (DDR_BASE + 0xE4) //DDR PHY Control 1 Register #define DDRCTL2 (DDR_BASE + 0xE8) //DDR PHY Control 2 Register #define DDRCTL3 (DDR_BASE + 0xEC) //DDR PHY Control 3 Register #define VTPIOCTL (DDR_BASE + 0xF0) //VTP IO Control register #define VTPIOSTAT (DDR_BASE + 0xF4) //VTP IO Status register // System Module Registers #define SYSTEM_MODULE_BASE_ADDR 0x01C40000 #define PINMUX0 (SYSTEM_MODULE_BASE_ADDR + 0x00) #define DSP_BOOT_ADDR_REG (SYSTEM_MODULE_BASE_ADDR + 0x08) #define HDVICPBOOT_REG (SYSTEM_MODULE_BASE_ADDR + 0x2C) #define VDD3P3VPWDN_REG (SYSTEM_MODULE_BASE_ADDR + 0x48) #define DSP_BOOT_ADDR 0x11818000 //PSC DDR #define LPSC_DDR_EMIF 20 /* DDR_EMIF LPSC */ #define LPSC_AEMIF 21 /* AEMIF LPSC */ #define LPSC_DSP 1 /* DSP LPSC */ #define LPSC_HDVICP0 2 /* HDVICP0 LPSC */ #define LPSC_HDVICP1 3 /* HDVICP1 LPSC */ #define PSC_BASE_ADDR 0x01C41000 #define EPCPR (PSC_BASE_ADDR+0x070) #define PTCMD (PSC_BASE_ADDR+0x120) #define PTSTAT (PSC_BASE_ADDR+0x128) #define PDSTAT (PSC_BASE_ADDR+0x200) #define PDCTL (PSC_BASE_ADDR+0x300) #define MDSTAT_DDR (PSC_BASE_ADDR+0x800+4*LPSC_DDR_EMIF) #define MDCTL_DDR (PSC_BASE_ADDR+0xA00+4*LPSC_DDR_EMIF) #define MDSTAT_AEMIF (PSC_BASE_ADDR+0x800+4*LPSC_AEMIF) #define MDCTL_AEMIF (PSC_BASE_ADDR+0xA00+4*LPSC_AEMIF) #define MDSTAT_DSP (PSC_BASE_ADDR+0x800+4*LPSC_DSP) #define MDCTL_DSP (PSC_BASE_ADDR+0xA00+4*LPSC_DSP) #define MDSTAT_HDVICP0 (PSC_BASE_ADDR+0x800+4*LPSC_HDVICP0) #define MDCTL_HDVICP0 (PSC_BASE_ADDR+0xA00+4*LPSC_HDVICP0) #define MDSTAT_HDVICP1 (PSC_BASE_ADDR+0x800+4*LPSC_HDVICP1) #define MDCTL_HDVICP1 (PSC_BASE_ADDR+0xA00+4*LPSC_HDVICP1) #define CSL_PSC_MDCTL_NEXT_MASK (0x0000001Fu) #define CSL_PSC_MDCTL_NEXT_SHIFT (0x00000000u) menuitem "DM6467_arm"; /*Bring DSP CPU out of Reset, Run from ARM*/ hotmenu BringDSPOutOfReset() { /*Release the DSP Reset*/ *(unsigned int*) MDCTL_DSP = *(unsigned int*) MDCTL_DSP | 0x100; GEL_TextOut("DSP CPU is Out of Reset \n"); } hotmenu PutDSPInReset() { /* Reset DSP */ *(unsigned int*) MDCTL_DSP = *(unsigned int*) MDCTL_DSP & 0x0FF; GEL_TextOut("DSP CPU is in Reset Mode\n"); } /* Bring HDVICP0 out of Reset */ BringHDVICP0OutOfReset() { /* Enable HDVICP0 LPSC */ lpscEnable(LPSC_HDVICP0); /* Release the HDVICP0 Reset */ *(unsigned int*) MDCTL_HDVICP0 = *(unsigned int*) MDCTL_HDVICP0 | 0x100; GEL_TextOut("HDVICP0 is Out of Reset \n"); } hotmenu PutHDVICP0InReset() { /* Reset HDVICP0 */ *(unsigned int*) MDCTL_HDVICP0 = *(unsigned int*) MDCTL_HDVICP0 & 0x0FF; GEL_TextOut("HDVICP0 is in Reset Mode\n"); } /* Bring HDVICP1 out of Reset */ BringHDVICP1OutOfReset() { /* Enable HDVICP1 LPSC */ lpscEnable(LPSC_HDVICP1); /* Release the HDVICP1 Reset */ *(unsigned int*) MDCTL_HDVICP1 = *(unsigned int*) MDCTL_HDVICP1 | 0x100; GEL_TextOut("HDVICP1 is Out of Reset \n"); } hotmenu PutHDVICP1InReset() { /* Reset HDVICP1 */ *(unsigned int*) MDCTL_HDVICP1 = *(unsigned int*) MDCTL_HDVICP1 & 0x0FF; GEL_TextOut("HDVICP1 is in Reset Mode\n"); } hotmenu DSPBootFromL2ByARM() { unsigned int PdNum = 0, k=0, domainOn = 0; /*Program the DSP Boot Address*/ *(unsigned int*) DSP_BOOT_ADDR_REG = DSP_BOOT_ADDR; *(unsigned int*) MDCTL_DSP = *(unsigned int*) MDCTL_DSP | 0x3; /* Make sure Power Domain 0 (Always On) is ON */ domainOn = (*(unsigned int*) PDSTAT) & 0x00000001; if(domainOn == 0) { GEL_TextOut("ERR: Power Domain 0 is not ON\n"); } *(unsigned int*) PTCMD = (1<> PdNum) & 0x00000001) == 0)); while(!((*(unsigned int*)MDSTAT_DSP & 0x0000001F) == 0x3)); /*Branch to itself*/ GEL_MemoryFill(DSP_BOOT_ADDR, 0, 0x20, 0x13); /* Release the DSP Reset */ *(unsigned int*) MDCTL_DSP = *(unsigned int*) MDCTL_DSP | 0x100; GEL_TextOut("DSP is Booted from L2RAM by ARM in Host Boot\n"); } //This routine enables a module (provides clocks) lpscEnable(lpscNum) { unsigned int lpscMdctl = 0, lpscMdstat = 0, PdNum = 0/* Domain0 */, mdCtlVal=0; /* Calculate MDCTL and MDSTAT reg addresses of the given LPSC */ lpscMdstat = (PSC_BASE_ADDR + 0x800) + 4 * lpscNum; lpscMdctl = (PSC_BASE_ADDR + 0xA00) + 4 * lpscNum; // Set NEXT = 0x3 to enable LPSC Module mdCtlVal = *(unsigned int*)lpscMdctl; *(unsigned int*) lpscMdctl = (mdCtlVal & ~CSL_PSC_MDCTL_NEXT_MASK) | ((0x3 << CSL_PSC_MDCTL_NEXT_SHIFT) & CSL_PSC_MDCTL_NEXT_MASK); // Program goctl to start transition sequence for LPSCs *(unsigned int*) PTCMD = (1 << PdNum); // Wait for GOSTAT = NO TRANSITION from LPSC while(! (((*(unsigned int*)PTSTAT >> PdNum) & 0x00000001) == 0)); // Wait for MODSTAT = ENABLE from LPSC while(!((*(unsigned int*)lpscMdstat & 0x0000001F) == 0x3)); // GEL_TextOut("Enabled LPSC Module = %d\n",,,,,lpscNum); } //This routine disables a module (gates clocks) lpscDisable(lpscNum) { unsigned int lpscMdctl = 0, lpscMdstat = 0, PdNum = 0/* Domain0 */, mdCtlVal=0; /* Calculate MDCTL and MDSTAT reg addresses of the given LPSC */ lpscMdstat = (PSC_BASE_ADDR + 0x800) + 4 * lpscNum; lpscMdctl = (PSC_BASE_ADDR + 0xA00) + 4 * lpscNum; // Set NEXT = 0x2 to disable LPSC Module mdCtlVal = *(unsigned int*)lpscMdctl; *(unsigned int*) lpscMdctl = (mdCtlVal & ~CSL_PSC_MDCTL_NEXT_MASK) | ((0x2 << CSL_PSC_MDCTL_NEXT_SHIFT) & CSL_PSC_MDCTL_NEXT_MASK); // Program goctl to start transition sequence for LPSCs *(unsigned int*) PTCMD = (1 << PdNum); // Wait for GOSTAT = NO TRANSITION from LPSC while(! (((*(unsigned int*)PTSTAT >> PdNum) & 0x00000001) == 0)); // Wait for MODSTAT = ENABLE from LPSC while(!((*(unsigned int*)lpscMdstat & 0x0000001F) == 0x2)); // GEL_TextOut("Disabled LPSC Module = %d\n",,,,,lpscNum); } lpscSyncReset(lpscNum) { unsigned int lpscMdctl = 0, lpscMdstat = 0, PdNum = 0/* Domain0 */, mdCtlVal=0; /* Calculate MDCTL and MDSTAT reg addresses of the given LPSC */ lpscMdstat = (PSC_BASE_ADDR + 0x800) + 4 * lpscNum; lpscMdctl = (PSC_BASE_ADDR + 0xA00) + 4 * lpscNum; // Set NEXT = 0x1 to sync reset LPSC Module mdCtlVal = *(unsigned int*)lpscMdctl; *(unsigned int*) lpscMdctl = (mdCtlVal & ~CSL_PSC_MDCTL_NEXT_MASK) | ((0x1 << CSL_PSC_MDCTL_NEXT_SHIFT) & CSL_PSC_MDCTL_NEXT_MASK); // Program goctl to start transition sequence for LPSCs *(unsigned int*) PTCMD = (1 << PdNum); // Wait for GOSTAT = NO TRANSITION from LPSC while(! (((*(unsigned int*)PTSTAT >> PdNum) & 0x00000001) == 0)); // Wait for MODSTAT = ENABLE from LPSC while(!((*(unsigned int*)lpscMdstat & 0x0000001F) == 0x1)); // GEL_TextOut("Sync Reset LPSC Module = %d\n",,,,,lpscNum); } /* This function powers up 3.3V I/O cells of all modules */ hotmenu VDD_3P3V_PowerUp() { /* Power up 3.3V I/O cells of all modules */ *(unsigned int*)VDD3P3VPWDN_REG = 0x0; GEL_TextOut("Powered up 3.3V I/O cells of all modules.\n"); } // Enable all LPSC modules hotmenu lpscEnableAll() { unsigned int lpscNum = 0; unsigned int lpsc_start = 0; unsigned int lpsc_end = 35; /* Skip locked LPSCs [36-44] */ GEL_TextOut("All LPSC Modules are getting enabled...Wait...\n"); /* Enable all LPSC modules */ for(lpscNum = lpsc_start; lpscNum <= lpsc_end; lpscNum++) { lpscEnable(lpscNum); } GEL_TextOut("Skip locked LPSCs [36-44].\n"); lpscEnable(45); /* AINTC - Last LPSC(45) in the list */ GEL_TextOut("DONE: All LPSC Modules are Enabled.\n"); /* Power up 3.3V I/O cells of all modules */ VDD_3P3V_PowerUp(); } hotmenu EnableHDVICP0_1() { unsigned int delay; GEL_TextOut("Enabling HDVICP0 and HDVICP1...Wait...\n"); // First bring HDVICP0 and HDVICP1 out of reset. BringHDVICP0OutOfReset(); BringHDVICP1OutOfReset(); /* Enable IAHB Fetch and Internal TCM */ *(unsigned int *) (HDVICPBOOT_REG) = 0x00100010; /* Reset HDVICP0 */ lpscSyncReset(LPSC_HDVICP0); lpscEnable(LPSC_HDVICP0); /* Reset HDVICP1 */ lpscSyncReset(LPSC_HDVICP1); lpscEnable(LPSC_HDVICP1); GEL_TextOut("DONE: Enabled HDVICP0 and HDVICP1\n"); } menuitem "DM6467 DDR Configuration"; hotmenu DDR2ClkTurnOn() { unsigned int PdNum = 0, domainOn = 0; *(unsigned int*) MDCTL_DDR = *(unsigned int*) MDCTL_DDR | 0x3; /* Make sure Power Domain 0 (Always On) is ON */ domainOn = (*(unsigned int*) PDSTAT) & 0x00000001; if(domainOn == 0) { GEL_TextOut("ERR: Power Domain 0 is not ON\n"); } *(unsigned int*) PTCMD = (1<> PdNum) & 0x00000001) == 0)); while(!((*(unsigned int*)MDSTAT_DDR & 0x0000001F) == 0x3)); // DDR VTP Initialization // VTPIOCR = 0x00000002; // VTPIOCR register default value. VTP is powered up in dynamic update mode. *(unsigned int*) VTPIOCTL = 0x00000003; // Set VTP_RECAL bit. *(unsigned int*) VTPIOCTL = 0x00000002; // Toggle VTP_RECAL bit. // Wait for completion of VTP calibration and DDLL ready. while(!((*(unsigned int*)SDSTAT & 0x00000004) == 0x04)); // Wait for phy_dll_ready/PHYRDY bit set. lpscSyncReset(LPSC_DDR_EMIF); lpscEnable(LPSC_DDR_EMIF); GEL_TextOut("DDR2 Controller Clocks are Turned On and VTP initializaion Done\n"); } hotmenu DDR32bitInit_297MHZ() { //Program PHY Control Register *(unsigned int*) DDRCTL1 = 0x000080C7; // RL=7 //Program SDRAM Bank Config Register *(unsigned int*) SDCFG = 0x08D38A32; // CL=5, Bank=3 //Program SDRAM Timing Control Register *(unsigned int*) SDTIM0 = 0x4B245C12; *(unsigned int*) SDTIM1 = 0x3B2BC742; //Program SDRAM Bank Config Register *(unsigned int*) SDCFG = 0x08530A32; // Clear TIMUNLOCK bit //Program SDRAM Refresh Control Register *(unsigned int*) SDREF = 0x0000090D; // 7.8 x 297 = 2316.6 => 2317 GEL_TextOut("DDR2 init is done for 297MHz 32-bit Interface\n"); } hotmenu DDR32bitInit_310_5MHZ() { //Program PHY Control Register *(unsigned int*) DDRCTL1 = 0x000080C7; // RL=7 //Program SDRAM Bank Config Register *(unsigned int*) SDCFG = 0x08D38A32; // CL=5, Bank=3 //Program SDRAM Timing Control Register *(unsigned int*) SDTIM0 = 0x4F24645A; *(unsigned int*) SDTIM1 = 0x3B2DC742; //Program SDRAM Bank Config Register *(unsigned int*) SDCFG = 0x08530A32; // Clear TIMUNLOCK bit //Program SDRAM Refresh Control Register *(unsigned int*) SDREF = 0x00000976; // 7.8 x 310.5 = 2421.9 => 2422 GEL_TextOut("DDR2 init is done for 310.5MHz 32-bit Interface\n"); } menuitem "DM6467 AEMIF Configuration"; hotmenu AEMIFClksTurnOn() { unsigned int PdNum = 0, domainOn = 0; *(unsigned int*) MDCTL_AEMIF = *(unsigned int*) MDCTL_AEMIF | 0x3; /* Make sure Power Domain 0 (Always On) is ON */ domainOn = (*(unsigned int*) PDSTAT) & 0x00000001; if(domainOn == 0) { GEL_TextOut("ERR: Power Domain 0 is not ON\n"); } *(unsigned int*) PTCMD = (1<> PdNum) & 0x00000001) == 0)); while(!((*(unsigned int*)MDSTAT_AEMIF & 0x0000001F) == 0x3)); GEL_TextOut("AEMIF Controller Clocks are Turned On\n"); } hotmenu AEMIF16Init() { // Enable AEMIF Pinmux (PCIEN = 0 & HPIEN = 0 & ATAEN = 0) *(unsigned int*) PINMUX0 = *(unsigned int*) PINMUX0 & 0xFFFFFFF8; //ASYNC EMIF Configuration //Program Asynchronous Wait Cycles Configuration Control Register *(unsigned int*) WAITCFG = *(unsigned int*) WAITCFG | 0x0 ; //Program Asynchronous Bank1 Configuration Control Register *(unsigned int*) ACFG2 = 0x3FFFFFFD; //Program Asynchronous Bank2 Configuration Control Register *(unsigned int*) ACFG3 = 0x3FFFFFFD; //Program Asynchronous Bank3 Configuration Control Register *(unsigned int*) ACFG4 = 0x3FFFFFFD; //Program Asynchronous Bank4 Configuration Control Register *(unsigned int*) ACFG5 = 0x3FFFFFFD; GEL_TextOut("AEMIF init is done for 16-bit Interface\n"); } /******************************************************** * DM6467 PLL Initialization Code **********************************************************/ #define PLL1_BASE_ADDR 0x01C40800 #define PLL2_BASE_ADDR 0x01C40C00 /*PLL1 Controller Control Register=> Gerates clocks to DSP, ARM, VBUS, CFG, ETC*/ #define PLL1_PLLCTL (PLL1_BASE_ADDR + 0x100) /*PLL Control Register*/ #define PLL1_OCSEL (PLL1_BASE_ADDR + 0x104) /*OBSCLK Select Register*/ #define PLL1_SECCTL (PLL1_BASE_ADDR + 0x108) /*PLL Secondary Control Register*/ #define PLL1_PLLM (PLL1_BASE_ADDR + 0x110) /*PLL Multiplier Control Register*/ #define PLL1_PREDIV (PLL1_BASE_ADDR + 0x114) /*PLL Pre-Divider control Register*/ #define PLL1_PLLDVI1 (PLL1_BASE_ADDR + 0x118) /*PLL Controller Div1 Register*/ #define PLL1_PLLDVI2 (PLL1_BASE_ADDR + 0x11C) /*PLL Controller Div2 Register*/ #define PLL1_PLLDVI3 (PLL1_BASE_ADDR + 0x120) /*PLL Controller Div3 Register*/ #define PLL1_OSCDIV1 (PLL1_BASE_ADDR + 0x124) /*Oscilator Divider Register*/ #define PLL1_POSTDIV (PLL1_BASE_ADDR + 0x128) /*PLL Post-Divider Register*/ #define PLL1_BPDIV (PLL1_BASE_ADDR + 0x12C) /*Bypass Divider Register*/ #define PLL1_WAKEUP (PLL1_BASE_ADDR + 0x130) /*Wakeup Register*/ #define PLL1_PLLCMD (PLL1_BASE_ADDR + 0x138) /*PLL Controller Command Register*/ #define PLL1_PLLSTAT (PLL1_BASE_ADDR + 0x13C) /*PLL Controller Status Register*/ #define PLL1_ALNCTL (PLL1_BASE_ADDR + 0x140) /*PLL Controller Clock Align Control Register*/ #define PLL1_DCHANGE (PLL1_BASE_ADDR + 0x144) /*PLLDiv Ratio Change status Register*/ #define PLL1_CKEN (PLL1_BASE_ADDR + 0x148) /*Clock Enable Control Register*/ #define PLL1_CKSTAT (PLL1_BASE_ADDR + 0x14C) /*Clock Status Register*/ #define PLL1_SYSTAT (PLL1_BASE_ADDR + 0x150) /*SYSCLK Status Register*/ #define PLL1_PLLDIV4 (PLL1_BASE_ADDR + 0x160) /*PLL Controller Div4 Register*/ #define PLL1_PLLDIV5 (PLL1_BASE_ADDR + 0x164) /*PLL Controller Div5 Register*/ #define PLL1_PLLDIV6 (PLL1_BASE_ADDR + 0x168) /*PLL Controller Div6 Register*/ #define PLL1_PLLDIV7 (PLL1_BASE_ADDR + 0x16C) /*PLL Controller Div7 Register*/ #define PLL1_PLLDIV8 (PLL1_BASE_ADDR + 0x170) /*PLL Controller Div8 Register*/ #define PLL1_PLLDIV9 (PLL1_BASE_ADDR + 0x174) /*PLL Controller Div9 Register*/ /*PLL2 Controller Control Register=> Generages clocks to DDR2 PHY */ #define PLL2_PLLCTL (PLL2_BASE_ADDR + 0x100) /*PLL Control Register*/ #define PLL2_OCSEL (PLL2_BASE_ADDR + 0x104) /*OBSCLK Select Register*/ #define PLL2_SECCTL (PLL2_BASE_ADDR + 0x108) /*PLL Secondary Control Register*/ #define PLL2_PLLM (PLL2_BASE_ADDR + 0x110) /*PLL Multiplier Control Register*/ #define PLL2_PREDIV (PLL2_BASE_ADDR + 0x114) /*PLL Pre-Divider control Register*/ #define PLL2_PLLDIV1 (PLL2_BASE_ADDR + 0x118) /*PLL Controller Div1 Register*/ #define PLL2_PLLDIV2 (PLL2_BASE_ADDR + 0x11C) /*PLL Controller Div2 Register*/ #define PLL2_PLLDIV3 (PLL2_BASE_ADDR + 0x120) /*PLL Controller Div3 Register*/ #define PLL2_OSCDIV1 (PLL2_BASE_ADDR + 0x124) /*Oscilator Divider Register*/ #define PLL2_POSTDIV (PLL2_BASE_ADDR + 0x128) /*PLL Post-Divider Register*/ #define PLL2_BPDIV (PLL2_BASE_ADDR + 0x12C) /*Bypass Divider Register*/ #define PLL2_WAKEUP (PLL2_BASE_ADDR + 0x130) /*Wakeup Register*/ #define PLL2_PLLCMD (PLL2_BASE_ADDR + 0x138) /*PLL Controller Command Register*/ #define PLL2_PLLSTAT (PLL2_BASE_ADDR + 0x13C) /*PLL Controller Status Register*/ #define PLL2_ALNCTL (PLL2_BASE_ADDR + 0x140) /*PLL Controller Clock Align Control Register*/ #define PLL2_DCHANGE (PLL2_BASE_ADDR + 0x144) /*PLLDiv Ratio Change status Register*/ #define PLL2_CKEN (PLL2_BASE_ADDR + 0x148) /*Clock Enable Control Register*/ #define PLL2_CKSTAT (PLL2_BASE_ADDR + 0x14C) /*Clock Status Register*/ #define PLL2_SYSTAT (PLL2_BASE_ADDR + 0x150) /*SYSCLK Status Register*/ menuitem "DM6467_PLL_Initialization"; /* System PLL Initialization in Normal mode with Clkin as the reference input */ hotmenu SystemPLL_NormalMode_ClkIn() { unsigned int i=0; unsigned int GOSTAT; unsigned int CLKSRC=1; /* CLKSRC=1 => External Clock CLKSRC=0 => Onchip oscillator */ unsigned int PLL_INPUT=27; /* PLL input clock */ unsigned int PLL_MULTI=26; /* NORMAL MODE (27MHz x 27 = 729MHz) */ GEL_TextOut("Please wait System PLL initialization in Normal Mode is in Progress...Wait.....\n"); /* Select the Clock Mode as External Clock */ *(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL | (CLKSRC<<8); /* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR */ *(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL & 0xFFFFFFDF; /* Set PLL Bypass Mode (Set PLLEN=0) */ *(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL & 0xFFFFFFFE; /* Wait for few cycles to allow PLLEN mux switches properly to bypass clock */ for(i=0; i<40; i++) {} /* 1 cycle : 27MHz (37ns) */ /* Wait : 37ns * 20 = 740(ns) */ /* Wait for few cycles to allow PLLEN Mux Switches */ /* properly to bypass clock */ /* Reset the PLL */ *(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL | 0x8; /* Disable the PLL */ *(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL | 0x10; /* --------------------------- */ /* PLL Initialization Sequence */ /* --------------------------- */ /* Power up the PLL */ *(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL & 0xFFFFFFFD; /* Enable the PLL from Disable Mode */ *(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL & 0xFFFFFFEF; for(i=0; i<4196; i++) {} /* Stabilization TIme : 150us */ /* 1 cycle : 1/27MHz */ /* Wait : 1/27MHz * 4096 = 151.7ns */ /* Set PLLM (x22) [Normal Mode] (27MHz x 22 = 594MHz) */ *(unsigned int*) PLL1_PLLM = PLL_MULTI; /* ------------------------- */ /* Program PLLDIV Registers */ /* ------------------------- */ // Wait for pending (if any) GO command GOSTAT = *(unsigned int*) PLL1_PLLSTAT & 0x1; while(GOSTAT==1) { GOSTAT = *(unsigned int*) PLL1_PLLSTAT & 0x1; } // Set SYSCLK4 (ATA) Divider Value *(unsigned int*)PLL1_PLLDIV4 = *(unsigned int*)PLL1_PLLDIV4 & 0xfffffff0; *(unsigned int*)PLL1_PLLDIV4 |= 6; //ATA: 104.14MHz // Set SYSCLK5 (TSIF0) Divider Value *(unsigned int*)PLL1_PLLDIV5 = *(unsigned int*)PLL1_PLLDIV5 & 0xfffffff0; *(unsigned int*)PLL1_PLLDIV5 |= 9; //TSIF0: 72.9MHz // Set SYSCLK6 (TSIF1) Divider Value *(unsigned int*)PLL1_PLLDIV6 = *(unsigned int*)PLL1_PLLDIV6 & 0xfffffff0; *(unsigned int*)PLL1_PLLDIV6 |= 9; //TSIF1: 72.9MHz // Set SYSCLK8 (VPIF) Divider Value *(unsigned int*)PLL1_PLLDIV8 = *(unsigned int*)PLL1_PLLDIV8 & 0xfffffff0; *(unsigned int*)PLL1_PLLDIV8 |= 9; //VPIF: 72.9MHz // Set SYSCLK9 (VLYNQ) Divider Value *(unsigned int*)PLL1_PLLDIV9 = *(unsigned int*)PLL1_PLLDIV9 & 0xfffffff0; *(unsigned int*)PLL1_PLLDIV9 |= 6; //VLYNQ: 104.14MHz *(unsigned int*) PLL1_PLLCMD |= 0x1; // Let "GO" command finish GOSTAT = *(unsigned int*) PLL1_PLLSTAT & 0x1; while(GOSTAT==1) { GOSTAT = *(unsigned int*) PLL1_PLLSTAT & 0x1; } /* Wait min 32 cycles */ for(i=0; i<100; i++) {} /* Bring PLL out of Reset */ *(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL & 0xFFFFFFF7; /* Wait for PLL to LOCK atleast 2000 MXI clock or Reference clock cycles */ for(i=0; i<3100; i++) {} /* Lock Time : 2000 cycles */ /* Allow 2000 Reference Clock to Lock */ /*Enable the PLL Bit of PLLCTL*/ *(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL | 0x1; GEL_TextOut("DONE: System PLL is Initialized at %d * %d = %dMHz\n",,,,,PLL_INPUT, (PLL_MULTI+1), (PLL_INPUT * (PLL_MULTI+1))); } /* DDR PLL Initialization in Normal mode with Clkin as the reference input */ hotmenu DDRPLL_NormalMode_ClkIn() { unsigned int i=0; unsigned int CLKSRC=1; /* CLKSRC=1 => External Clock CLKSRC=0 => Onchip oscillator */ unsigned int PLL_INPUT=27; /* PLL input clock */ unsigned int PLL_MULTI=22; /* DDR2 Clock = 27 * 23 = 621MHz */ GEL_TextOut("Pleae wait DDR PLL initialization in Normal Mode is in Progress...Wait.....\n"); /* Select the Clock Mode as External Clock */ *(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL | (CLKSRC<<8); /* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR */ *(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL & 0xFFFFFFDF; /* Set PLL Bypass Mode (Set PLLEN=0) */ *(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL & 0xFFFFFFFE; /* Wait for few cycles to allow PLLEN mux switches properly to bypass clock */ for(i=0; i<40*11; i++) {} /* 1 cycle : 27MHz (37ns) */ /* Wait : 37ns * 20 = 740(ns) */ /* Wait for few cycles to allow PLLEN Mux Switches */ /* properly to bypass clock */ /* Reset the PLL */ *(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL | 0x8; /* Disable the PLL */ *(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL | 0x10; /* --------------------------- */ /* PLL Initialization Sequence */ /* --------------------------- */ /* Power up the PLL */ *(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL & 0xFFFFFFFD; /* Enable the PLL from Disable Mode */ *(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL & 0xFFFFFFEF; for(i=0; i<4196*11; i++) {} /* Stabilization TIme : 150us */ /* 1 cycle : 1/27MHz */ /* Wait : 1/27MHz * 4096 = 151.7ns */ /* Set PLLM (x22) [Normal Mode] (27MHz x 22 = 594MHz) */ *(unsigned int*) PLL2_PLLM = PLL_MULTI; /* ------------------------- */ /* Program PLLDIV Registers */ /* ------------------------- */ /* No PLLDIV configuration needed */ /* Wait min 32 cycles */ for(i=0; i<100*11; i++) {} /* Bring PLL out of Reset */ *(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL & 0xFFFFFFF7; /* Wait for PLL to LOCK atleast 2000 MXI clock or Reference clock cycles */ for(i=0; i<3100*11; i++) {} /* Lock Time : 2000 cycles */ /* Allow 2000 Reference Clock to Lock */ /*Enable the PLL Bit of PLLCTL*/ *(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL | 0x1; GEL_TextOut("DONE: DDR PLL is Initialized at %d * %d = %dMHz\n",,,,,PLL_INPUT, (PLL_MULTI+1), (PLL_INPUT * (PLL_MULTI+1))); } StartUp(){ SystemPLL_NormalMode_ClkIn(); DDRPLL_NormalMode_ClkIn(); DDR2ClkTurnOn(); DDR32bitInit_310_5MHZ(); }