DaVinciHD Test Cases
====================

Primary Testing[P1]:
--------------------

[ARM JTAG]]     [Pass] -> Check pin & signals are connected.

[Emulation]     [Pass] -> Check JTAG Scan Chain looks like ARM926 & C64x+
                [Pass] -> Verify ARM926 connects to CCS
                [Pass] -> Verify C64x+ connects to CCS

[BootMode]      [Pass] -> Bootmode switch [SW3] works and can set boot mode settings

[PLL0]          [Pass] -> Set PLL 0 freq to [DSP:594MHz] [ARM:297MHz]

[PLL1]          [Pass] -> Set PLL 1 freq to [DDR2:###MHz]
                [Pass] -> PLL1 freq 148.5 MHz
                [Pass] -> PLL1 freq 216.0 MHz
                [Pass] -> PLL1 freq 265.5 MHz
                [Pass] -> PLL1 freq 270.0 MHz
                [Pass] -> PLL1 freq 283.5 MHz

[PSC]           [Pass] -> Setup all Non-Reserved Power Modules to ENABLED state

[DDR2]          [Pass] -> Setup DDR2 Phy to work with [DDR2 freq ### MHz].
[DDR2]          [Pass] -> Test DDR2 Data & Address lines [256 MBytes range]
                [Pass] -> DDR freq 148.5 MHz
                [Pass] -> DDR freq 216.0 MHz
                [Pass] -> DDR freq 265.5 MHz
                [Pass] -> DDR freq 270.0 MHz
                [Pass] -> DDR freq 283.5 MHz
                [Pass] -> DDR freq 297.0 MHz

[NAND]          [Pass] -> Test NAND Flash Block 0 / Page 0 [Erase/Write/Read]
                [Pass] -> Test NAND Flash memory [Erase/Write/Read][128 MBytes]
                [Pass] -> EMIF mode. Does not use NAND Flash Control Reg [0x20008060]

Secondary Testing[P2]:
----------------------

[I2C EEPROM]    [Pass] -> Run I2C EEPROM test [Write/Read] [I2C address 0x50]

[I2C LEDs]      [Pass] -> Run LED test [I2C address 0x38]

[I2C DIPs]      [Pass] -> Run DIP switch test [I2C address 0x38]

[I2C CPLD]      [Pass] -> Run CPLD test [I2C addresses 0x3a, 0x3b, 0x3c].
                [Pass] -> Check to see if registers are readable/writeable.

[UART RS232]    [Pass] -> Run RS232 loopback test 
                [Pass] -> Connected RS232 through NULL cable to PC with hyperterminal session at 115200 baudrate

[EMAC GMII]    *(Added more capacitance to PHY core regulators)
               *(Direction of LEDs on RJ45 jack is backwards)
               *(TX_ER signal should be grounded)
                [Pass] -> EMAC MII mode test at 100 Mbits (64 byte packets)
                [Pass] -> EMAC GMII mode test at 1Gbit (64 byte packets)

[MAC address]   [Pass] -> Set MAC address

[CDCE949]       [Pass] -> Can set input to use VCXO
                [Pass] -> Can set CDCE949 to output 74.25MHz for Video HD test

[VCXO]          [Pass] -> Test PWM & TMR modules connected to the CDCE949 PLL.
                [Pass] -> Verify VCXO works on CDCE949.

[Video SD]     *(Synchronize issue fixed by using synchronizing the frame syncs on Channels 0&1 with Channels 2&3)
                [Pass] -> [Composite] Hardware Video output [Colorbars] from ADV7343 (NTSC:480I)
                [Pass] -> [S-Video]   Hardware Video output [Colorbars] from ADV7343 (NTSC:480I)
                [Pass] -> Software Video Output [Colorbars] from DaVinci chip (NTSC:480I)

[Video HD]     *(Requires 37.5 Ohm pulldowns on R168, R169, R170)
                [Pass] -> [Component] Hardware Video output [Full Screen Color] from ADV7343 (HDTV:720P)
                [Pass] -> [Component] Hardware Video output [Full Screen Color] from ADV7343 (HDTV:1080I)
                [Pass] -> Software Video Output [Colorbars] from DaVinci chip (HDTV:1080I)
                [Pass] -> Software Video Output [Colorbars] from DaVinci chip (HDTV:720P)

[Audio]         *(Headphone jack needs to be grounded)
                [Pass] -> Audio codec can output 1KHz tone on headphone and lineout
                [Pass] -> Audio codec can playback linein and micin to headphone and lineout

Tertiary Testing[P3]:
---------------------

[PCI]           [Pass] -> Verify PCI boot mode works
                [Pass] -> Check that PCI IDs 
                [Pass] -> Write and Read back PCI registers

[VLYNQ]         [Pass] -> VLYNQ loopback test (4 TX/RX pin)(49.5 MHz Clock)

[ATA Power]     [Pass] -> ATA reset can be turned On & Off from (CPLD Reg0[0])
                [Pass] -> ATA power can be turned On & Off from (CPLD Reg0[1])

[ATA]           (Tested using Toshiba Disk Drive MK4032GAX 40 GB)
                [Pass] -> ATA test in PIO mode
                [Pass] -> ATA test in Multi-word DMA mode
                [Pass] -> ATA test in Ultra DMA mode

[USB Power]     [Pass] -> Test +5V USB power (GPIO22)
                [Pass] -> Test +5V USB feedback work (GPIO4)

[Ir Remote]     *(Need new IR sensor QSE156)
                [Pass] -> Test UART-CIR using Ir remote control

[Video SD]      [Pass] -> [Composite -> Composite + SVideo] SW Video Loopback input from TVP5147_1
                [Pass] -> [SVideo    -> Composite + SVideo] SW Video Loopback input from TVP5147_0

[Video HD]      *(Video Color issue fixed using new THS7353)
                *(THS7353 settings for Channel 1(Red) & 3(Blue) are using input bias: 4-AC Bias Select)
                *(THS7353 settings for Channel 2(Green) is using input bias: 5-Sync Tip Clamp low bias)
                [Pass] -> [Component -> Component] SW Video Loopback input from TVP7002_1 (HDTV:720P)
                [Pass] -> [Component -> Component] SW Video Loopback input from TVP7002_1 (HDTV:1080I)

[SPIROM]        [Pass] -> Read/write to SPI EEPROM

[SPDIF]         *(Sending raw binary data to SPDIF connectors, not SPDIF encoded data)
                [Pass] -> Check SPDIF output on connectors
                [Pass] -> Test SPDIF output from McASP1